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D a t a S h e e t , V 1 . 0 , A p r . 2 0 08
TC1163/TC1164
32-Bit Single-Chip Microcontroller TriCore
Microcontrollers
Edition 2008-04 Published by Infineon Technologies AG 81726 Munchen, Germany
(c) Infineon Technologies AG 2008. All Rights Reserved.
Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of noninfringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S h e e t , V 1 . 0 , A p r . 2 0 08
TC1163/TC1164
32-Bit Single-Chip Microcontroller TriCore
Microcontrollers
TC1163/TC1164
Preliminary
TC1163/TC1164 Data Sheet Revision History: V1.0, 2008-04 Previous Version: V0.3 2007-03 Page 7 8, 10 Subjects (major changes since last revision) VSSOSC3 is deleted from the TC1163/TC1164 Logic Symbol. TDATA0 of Pin 17, TCLK0 of Pin 20, TCLK0 of Pin 74 and TDATA0 of Pin 77 are updated in the Pinning Diagram and Pin Definition and Functions Table. Transmit DMA request in Block Diagram of ASC Interfaces is updated. Alternate output functions in block diagram of SSC interfaces are updated. Programmable baud rate of the MLI is updated. TDATA0 and TCLK0 of the block diagram of MLI interfaces are updated. The description for WDT double reset detection is updated. The power sequencing details is updated. MLI timing, maximum operating frequency limit is extended, t31 is added. Thermal resistance junction leads is updated.
53 55 61 62 74 111 122 126 Trademarks
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Data Sheet
V1.0, 2008-04
TC1163/TC1164
Preliminary Table of Contents
Table of Contents
1 2 2.1 2.2 2.3 2.4 2.5 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.4.1 3.3.4.2 3.3.5 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.13.1 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pad Driver and Input Classes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Architecture and On-Chip Bus Systems . . . . . . . . . . . . . . . . . . . . On-Chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architectural Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Read the Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents of the Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Map of the FPI Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . Segments 0 to 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Segment 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Map of the Local Memory Bus (LMB) . . . . . . . . . . . . . . . . . . . Memory Protection System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Control Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Controller and Memory Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1) . . . . . . . . . . High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) . . . . . . . . . Micro Second Bus Interface (MSC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MultiCAN Controller (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Micro Link Serial Bus Interface (MLI0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Timer Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functionality of GPTA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter (ADC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Analog-to-Digital Converter Unit (FADC) . . . . . . . . . . . . . . . . . . . . . . System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Identification Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
24 24 25 27 27 29 30 32 32 37 42 46 46 49 51 53 55 57 59 61 63 64 67 69 71 74 75 76 77 78 80 83 84
Data Sheet
V1.0, 2008-04
TC1163/TC1164
Preliminary 4 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.8.1 4.3.8.2 4.3.8.3 5 5.1 5.2 5.3 5.4 Table of Contents
Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . 87 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Analog to Digital Converter (ADC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Fast Analog to Digital Converter (FADC) . . . . . . . . . . . . . . . . . . . . . . . 102 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Power, Pad and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Debug Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Timing for JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Micro Link Interface (MLI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Micro Second Channel (MSC) Interface Timing . . . . . . . . . . . . . . . 124 Synchronous Serial Channel (SSC) Master Mode Timing . . . . . . . . 125 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters (PG-LQFP-176-2) . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 126 127 128 129
Data Sheet
2
V1.0, 2008-04
TC1163/TC1164
Preliminary Summary of Features
1
*
Summary of Features
High-performance 32-bit super-scaler TriCore v1.3 CPU with 4-stage pipeline - Superior real-time performance - Strong bit handling - Fully integrated DSP capabilities - Single precision Floating Point Unit (FPU) - 80 MHz operation at full temperature range Peripheral Control Processor with single cycle instruction (PCP2) - 8 Kbyte Parameter Memory (PRAM) - 12 Kbyte Code Memory (CMEM) Multiple on-chip memories - 40 Kbyte Local Data Memory (SRAM) - 8 Kbyte Overlay Memory - 8 Kbyte Scratch-Pad RAM (SPRAM) - 8 Kbyte Instruction Cache (ICACHE) - 1024 Kbyte Program Flash (for instruction code and constant data) - 16 Kbyte Data Flash (e.g. 2 Kbyte EEPROM emulation) - 16 Kbyte Boot ROM 8-channel DMA Controller Fast-response interrupt system with 2 x 255 hardware priority arbitration levels serviced by CPU or PCP2 High-performance on-chip bus structure - 64-bit Local Memory Bus (LMB) to Flash memory - System Peripheral Bus (SPB) for interconnections of functional units Versatile on-chip Peripheral Units - Two Asynchronous/Synchronous Serial Channels (ASCs) with baudrate generator, parity, framing and overrun error detection - Two High Speed Synchronous Serial Channels (SSCs) with programmable data length and shift direction - One Micro Second Bus (MSC) interface for serial port expansion to external power devices - One high-speed Micro Link Interface (MLI) for serial inter-processor communication - One MultiCAN Module with two CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer1)
The TC1163/TC1164 has the following features:
*
*
* * *
*
1) Not applicable to TC1163
Data Sheet
3
V1.0, 2008-04
TC1163/TC1164
Preliminary Summary of Features
* * * * * * * * * *
- One General Purpose Timer Array Module (GPTA) with a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management - One 16-channel Analog-to-Digital Converter unit (ADC) with selectable 8-bit, 10bit, or 12-bit, supporting 32 input channels - One 2-channel Fast Analog-to-Digital Converter unit (FADC) with concatenated comb filters for hardware data reduction: supporting 10-bit resolution, with minimum conversion time of 262.5ns 32 analog input lines for ADC and FADC 81 digital general purpose I/O lines Digital I/O ports with 3.3 V capability On-chip debug support for OCDS Level 1 and 2 (CPU, PCP, DMA) Power Management System Clock Generation Unit with PLL Core supply voltage of 1.5 V I/O voltage of 3.3 V Full Industrial and Multi-Market temperature range: -40 to +85C PG-LQFP-176-2 package
Data Sheet
4
V1.0, 2008-04
TC1163/TC1164
Preliminary Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: * * The derivative itself, i.e. its function set, the temperature range, and the supply voltage The package and the type of delivery Summary of Features
For the available ordering codes for the TC1163/TC1164, please refer to the "Product Catalog Microcontrollers" that summarizes all available microcontroller variants. This document describes the derivatives of the device.The Table 1-1 enumerates these derivatives and summarizes the differences. Table 1-1 Derivative SAF-TC1163-128F80HL SAF-TC1164-128F80HL TC1163/TC1164 Derivative Synopsis Ambient Temperature Range TA = -40oC to +85oC TA = -40oC to +85oC
Data Sheet
5
V1.0, 2008-04
TC1163/TC1164
Preliminary General Device Information
2
General Device Information
Chapter 2 provides the general information for the TC1163/TC1164.
2.1
Block Diagram
Figure 2-1 shows the TC1163/TC1164 block diagram.
PMI 8 KB SPRAM 8 KB ICACHE
FPU TriCore (TC1.3M) CPS
DMI 40 KB LDRAM
Local Memory Bus (LMB) PMU 16 KB BROM 1024 KB Pflash 16 KB DFlash 8 KB OVRAM Overl ay Me chan ism LBCU LFI Bridge
Abbreviations: ICACHE: SPRAM: LDRAM: OVRAM: BROM: PFlash: DFlash: PRAM: CMEM:
Instruction Cache Scratch-Pad RAM Local Data RAM Overlay RAM Boot ROM Program Flash Data Flash Parameter Memory in PCP Code Memory in PCP
8 KB PRAM Interru pts OCDS Debug Interface/JTAG System Peri phe ral Bus (SPB) FPI-Bus Interface
PCP2 Core
STM
ASC0
SBCU DMA Bus 12 KB CMEM Ports SSC0
ASC1
SCU
PLL PLL
f FPI f CPU
SSC1
8 ch. SMIF
Ext. Request Unit
Multi CAN (2 Nodes, 64 Buffer)
1)
FADC 2 ch.
MSC0 Mem Check
MLI0
1) Not applicable to TC1163
TC1163/TC1164 Block Diagram
Figure 2-1
TC1163/TC1164 Block Diagram
Data Sheet
6
Ana log Inp ut Assi gnme nt
GPTA
DMA BI0 BI1
ADC0 32 ch.
V1.0, 2008-04
TC1163/TC1164
Preliminary General Device Information
2.2
Logic Symbol
Figure 2-2 shows the TC1163/TC1164 logic symbol.
Alternate Functions PORST HDRST General Control NMI BYPASS TESTMODE FCLP 0A FCLN0 MSC0 Control SOP0A SON0 AN[35:0] VDDM VSSM V DDMF ADC/FADC Analog Power Supply VSSMF V DDAF VSSAF V AREF0 VAGND0 VFAREF VFAGND VDDFL3 Digital Circuitry Power Supply VDD VDDP V SS TC1163/ TC1164 Port 0 16-bit Port 1 15-bit Port 2 14-bit Port 3 16-bit Port 4 4-bit Port 5 16-bit TRST TCK TDI TDO TMS BRKIN BRKOUT TRCLK XTAL1 XTAL2 VDDOSC3 GPTA, SCU GPTA, SSC1, ADC SSC0/1, MLI0, GPTA, MSC0 ASC0/1, SSC0/1, SCU, CAN GPTA, SCU GPTA, OCDS L 2, MLI0
1)
ADC Analog Inputs
OCDS / JTAG Control
7 8 9
VDDOSC VSSOSC
Oscillator
TC1163/TC1164 Logic Symbol
1) Alternate functions for CAN module is not applicable for TC 1163.
Figure 2-2
TC1163/TC1164 Logic Symbol
Data Sheet
7
V1.0, 2008-04
TC1163/TC1164
Preliminary General Device Information
2.3
Pin Configuration
Figure 2-3 shows the TC1163/TC1164 pin configuration.
P0.15/IN15/SWCFG15/REQ5/OUT15/OUT71 P0.14/IN14/SWCFG14/REQ4/OUT14/OUT70 P0.7/IN7/SWCFG7/REQ3/OUT7/OUT63 P0.6/IN6/SWCFG6/REQ2/OUT6/OUT62 VSS VDDP VDD P0.13/IN13/SWCFG13/OUT13/OUT69 P0.12/IN12/SWCFG12/OUT12/OUT68 P0.5/IN5/SWCFG5/OUT5/OUT61 P0.4/IN4/SWCFG4/OUT4/OUT60 P2.13/SLSI1/SDI0 P2.8/SLSO04/SLSO14/EN00 P2.12/MTSR1A/SOP0B P2.11/SCLK1A/FCLP0B P2.10/MRST1A P2.9/SLSO05/SLSO15/EN01 SOP0A SON0 FCLP0A FCLN0 VSS VDDP VDD P0.11/IN11/SWCFG11/OUT11/OUT67 P0.10/IN10/SWCFG10/OUT10/OUT66 P0.9/IN9/SWCFG9/OUT9/OUT65 P0.8/IN8/SWCFG8/OUT8/OUT64 P0.3/IN3/SWCFG3/OUT3/OUT59 P0.2/IN2/SWCFG2/OUT2/OUT58 P0.1/IN1/SWCFG1/OUT1/OUT57 P0.0/IN0/SWCFG0/OUT0/OUT56 P3.11/REQ1 P3.12/RXDCAN01)/RXD0B P3.13/TXDCAN01)/TXD0B VDDFL3 VSS VDDP P3.9/RXD1A P3.10/REQ0 P3.0/RXD0A P3.1/TXD0A P3.14/RXDCAN11)/RXD1B P3.15/TXDCAN11)/TXD1B 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
OCDSDBG0/OUT40/IN40/P5.0 OCDSDBG1/OUT41/IN41/P5.1 OCDSDBG2/OUT42/IN42/P5.2 OCDSDBG3/OUT43/IN43/P5.3 OCDSDBG4/OUT44/IN44/P5.4 OCDSDBG5/OUT45/IN45/P5.5 OCDSDBG6/OUT46/IN46/P5.6 OCDSDBG7/OUT47/IN47/P5.7 TRCLK VDD VDDP VSS OCDSDBG8/RDATA0B/P5.8 OCDSDBG9/RVALID0B/P5.9 OCDSDBG10/RREADY0B/P5.10 OCDSDBG11/RCLK0B/P5.11 OCDSDBG12/TDATA0/P5.12 OCDSDBG13/TVALID0B/P5.13 OCDSDBG14/TREADY0B/P5.14 OCDSDBG15/TCLK0/P5.15 N.C. VSSAF VDDAF VDDMF VSSMF VFAREF VFAGND AN35 AN34 AN33 AN32 AN31 AN30 AN29 AN28 AN7 AN27 AN26 AN25 AN24 AN23 AN22 AN21 AN20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
TC1163/TC1164
P3.4/MTSR0 P3.7/SLSI0/SLSO02/SLSO12 P3.3/MRST0 P3.2/SCLK0 P3.8/SLSO06/TXD1A P3.6/SLSO01/SLSO11/SLSO01&SLSO11 P3.5/SLSO00/SLSO10/SLSO00&SLSO10 VSS VDDP VDD HDRST PORST NMI BYPASS TESTMODE BRKIN BRKOUT TCK TRST TDO TMS TDI P1.7/IN23/OUT23/OUT79 P1.6/IN22/OUT22/OUT78 P1.5/IN21/OUT21/OUT77 P1.4/IN20/EMG_IN/OUT20/OUT76 VDDOSC3 VDDOSC VSSOSC XTAL2 XTAL1 VSS VDDP VDD P1.3/IN19/OUT19/OUT75 P1.11/IN27/IN51/SCLK1B/OUT27/OUT51 P1.10/IN26/IN50/OUT26/OUT50/SLSO17 P1.9/IN25/IN49/MRST1B/OUT25/OUT49 P1.8/IN24/IN48/MTSR1B/OUT24/OUT48 P1.2/IN18/OUT18/OUT74 P1.1/IN17/OUT17/OUT73 P1.0/IN16/OUT16/OUT72 P4.3/IN31/IN55/OUT31/OUT55/SYSCLK N.C.
1) Not applicable to TC1163
AN19 AN18 AN17 AN16 AN15 AN14 VAGND0 VAREF0 VSSM VDDM AN13 AN12 AN11 AN10 AN9 AN8 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VDD VDDP VSS AD0EMUX2/P1.14 AD0EMUX1/P1.13 AD0EMUX0/P1.12 TCLK0/OUT32/IN32/P2.0 SLSO13/SLSO03/OUT33/TREADY0A/IN33/P2.1 TVALID0A/OUT34/IN34/P2.2 TDATA0/OUT35/IN35/P2.3 OUT36/RCLK0A/IN36/P2.4 RREADY0A/OUT37/IN37/P2.5 OUT38/RVALID0A/IN38/P2.6 OUT39/RDATA0A/IN39/P2.7 VSS VDDP VDD VSS OUT52/OUT28/HWCFG0/IN52/IN28/P4.0 OUT53/OUT29/HWCFG1/IN53/IN29/P4.1 OUT54/OUT30/HWCFG2/IN54/IN30/P4.2
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
TC1163/TC1164 Pinning
Figure 2-3
TC1163/TC1164 Pinning for PG-LQFP-176-2 Package
Data Sheet
8
V1.0, 2008-04
TC1163/TC1164
Preliminary General Device Information
2.4
Pad Driver and Input Classes Overview
The TC1163/TC1164 provides different types and classes of input and output lines. For understanding of the abbreviations in Table 2-2 starting at the next page, Table 2-1 gives an overview on the pad type and class types. Table 2-1 Class A Pad Driver and Input Classes Overview Type Sub Class Speed Grade 6 MHz 40 MHz Termination No Series termination recommended Yes, series termination Yes, series termination Parallel termination -
Power Supply 3.3V
LVTTL I/O, A1 (e.g. GPIO) LVTTL outputs A2 (e.g. serial I/Os) A3 (e.g. BRKIN, BRKOUT)
80 MHz/
A4 80 MHz (e.g.Trace Clock) C D 3.3V LVDS Analog input - - 50 MHz -
Data Sheet
9
V1.0, 2008-04
TC1163/TC1164
Preliminary General Device Information
2.5
Pin Definitions and Functions
Table 2-2 shows the TC1163/TC1164 pin definitions and functions. Table 2-2 Symbol Pin Definitions and Functions Pins I/O Pad Driver Class I/O A1 Power Functions Supply
Parallel Ports P0
VDDP
Port 0 Port 0 is a 16-bit bi-directional generalpurpose I/O port which can be alternatively used for GPTA I/O lines or external trigger inputs. IN0 / OUT0 / IN1 / OUT1 / IN2 / OUT2 / IN3 / OUT3 / IN4 / OUT4 / IN5 / OUT5 / IN6 / OUT6 / REQ2 IN7 / OUT7 / REQ3 IN8 / OUT8 / IN9 / OUT9 / IN10 / OUT10 / IN11 / OUT11 / IN12 / OUT12 / IN13 / OUT13 / IN14 / OUT14 / REQ4 IN15 / OUT15 / REQ5 OUT56 line of GPTA OUT57 line of GPTA OUT58 line of GPTA OUT59 line of GPTA OUT60 line of GPTA OUT61 line of GPTA OUT62 line of GPTA External trigger input 2 OUT63 line of GPTA External trigger input 3 OUT64 line of GPTA OUT65 line of GPTA OUT66 line of GPTA OUT67 line of GPTA OUT68 line of GPTA OUT69 line of GPTA OUT70 line of GPTA External trigger input 4 OUT71 line of GPTA External trigger input 5
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15
145 146 147 148 166 167 173 174 149 150 151 152 168 169 175 176
In addition, the state of the port pins are latched into the software configuration input register SCU_SCLIR at the rising edge of HDRST. Therefore, Port 0 pins can be used for operating mode selections by software.
Data Sheet
10
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 2-2 Symbol Pin Definitions and Functions (cont'd) Pins I/O Pad Driver Class I/O Power Functions Supply General Device Information
P1
VDDP
Port 1 Port 1 is a 15-bit bi-directional general purpose I/O port which can be alternatively used for GPTA I/O lines, SSC1 and ADC0 interface. IN16 / OUT16 / IN17 / OUT17 / IN18 / OUT18 / IN19 / OUT19 / IN20 / OUT20 / IN21 / OUT21 / IN22 / OUT22 / IN23 / OUT23 / IN24 / OUT24 / MTSR1B OUT72 line of GPTA OUT73 line of GPTA OUT74 line of GPTA OUT75 line of GPTA OUT76 line of GPTA OUT77 line of GPTA OUT78 line of GPTA OUT79 line of GPTA IN48 / OUT48 line of GPTA SSC1 master transmit output / slave rec. input B IN25 / OUT25 / IN49 / OUT49 line of GPTA MRST1B SSC1 master receive input / slave transmit output B IN26 / OUT26 / IN50 / OUT50 line of GPTA SLSO17 SSC1 slave select output 7 IN27 / OUT27 / IN51 / OUT51 line of GPTA SCLK1B SSC1 clock input / output B AD0EMUX0 ADC0 external multiplexer control output 0 AD0EMUX1 ADC0 external multiplexer control output 1 AD0EMUX2 ADC0 external multiplexer control output 2 In addition, P1.4 also serves as emergency shut-off input for certain I/O lines (e.g. GPTA related outputs).
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P1.8
91 92 93 98 107 108 109 110 94
A1 A1 A1 A1 A1 A1 A1 A1 A2
P1.9
95
A2
P1.10 P1.11 P1.12 P1.13 P1.14
96 97 73 72 71
A2 A2 A1 A1 A1
Data Sheet
11
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 2-2 Symbol Pin Definitions and Functions (cont'd) Pins I/O Pad Driver Class I/O Power Functions Supply General Device Information
P2
VDDP
Port 2 Port 2 is a 14-bit bi-directional generalpurpose I/O port which can be alternatively used for GPTA I/O, and interface for MLI0, MSC0 or SSC0/1. TCLK0 IN32 / OUT32 TREADY0A IN33 / OUT33 SLSO03 SLSO13 TVALID0A IN34 / OUT34 TDATA0 IN35 / OUT35 RCLK0A IN36 / OUT36 RREADY0A IN37 / OUT37 RVALID0A IN38 / OUT38 RDATA0A IN39 / OUT39 MLI0 transmit channel clock output A line of GPTA MLI0 transmit channel ready input A line of GPTA SSC0 slave select output 3 SSC1 slave select output 3 MLI0 transmit channel valid output A line of GPTA MLI0 transmit channel data output A line of GPTA MLI0 receive channel clock input A line of GPTA MLI0 receive channel ready output A line of GPTA MLI0 receive channel valid input A line of GPTA MLI0 receive channel data input A line of GPTA
P2.0
74
A2
P2.1
75
A2
P2.2
76
A2
P2.3
77
A2
P2.4
78
A1
P2.5
79
A2
P2.6
80
A1
P2.7
81
A1
Data Sheet
12
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 2-2 Symbol Pin Definitions and Functions (cont'd) Pins I/O Pad Driver Class 164 A2 Power Functions Supply SLSO04 SLSO14 EN00 SLSO05 SLSO15 EN01 MRST1A SCLK1A FCLP0B MTSR1A SOP0B SLSI1 SDI0 SSC0 Slave Select output 4 SSC1 Slave Select output 4 MSC0 enable output 0 SSC0 Slave Select output 5 SSC1 Slave Select output 5 MSC0 enable output 1 SSC1 master receive input / slave transmit output A SSC1 clock input/output A MSC0 clock output B SSC1 master transmit out / slave receive input A MSC0 serial data output B SSC1 slave select input MSC0 serial data input General Device Information
P2.8
P2.9
160
A2
P2.10 P2.11 P2.12
161 162 163
A2 A2 A2
P2.13
165
A1
Data Sheet
13
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 2-2 Symbol Pin Definitions and Functions (cont'd) Pins I/O Pad Driver Class I/O Power Functions Supply General Device Information
P3
VDDP
Port 3 Port 3 is a 16-bit bi-directional generalpurpose I/O port which can be alternatively used for ASC0/1, SSC0/1 and CAN lines. RXD0A TXD0A ASC0 receiver inp./outp. A ASC0 transmitter output A
P3.0 P3.1
136 135
A2 A2
This pin is sampled at the rising edge of PORST. If this pin and the BYPASS input pin are both active, then oscillator bypass mode is entered. P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 129 130 132 126 127 131 A2 A2 A2 A2 A2 A2 SCLK0 MRST0 MTSR0 SLSO00 SLSO10 SLSO01 SLSO11 SLSI0 SLSO02 SLSO12 SLSO06 TXD1A RXD1A REQ0 REQ1 RXDCAN01) RXD0B TXDCAN01) TXD0B RXDCAN11) RXD1B TXDCAN11) TXD1B SSC0 clock input/output SSC0 master receive input/ slave transmit output SSC0 master transmit output/slave receive input SSC0 slave select output 0 SSC1 slave select output 0 2) SSC0 slave select output 1 SSC1 slave select output 12) SSC0 slave select input SSC0 slave select output 2 SSC1 slave select output 2 SSC0 slave select output 6 ASC1 transmitter output A ASC1 receiver inp./outp. A External trigger input 0 External trigger input 1 CAN node 0 receiver input ASC0 receiver inp./outp. B CAN node 0 transm. output ASC0 transmitter output B CAN node 1 receiver input ASC1 receiver inp./outp. B CAN node 1 transm. output ASC1 transmitter output B
P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.14 P3.15
128 138 137 144 143 142 134 133
A2 A2 A1 A1 A2 A2 A2 A2
Data Sheet
14
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 2-2 Symbol Pin Definitions and Functions (cont'd) Pins I/O Pad Driver Class I/O Power Functions Supply General Device Information
P4 P4.[3:0]
VDDP
Port 4 / Hardware Configuration Inputs HWCFG[3:0] Boot mode and boot location inputs; inputs are latched with the rising edge of HDRST.
During normal operation, Port 4 pins may be used as alternate functions for GPTA or system clock output. P4.0 P4.1 P4.2 P4.3 86 87 88 90 A1 A1 A2 A2 IN28 / OUT28 / IN29 / OUT29 / IN30 / OUT30 / IN31 / OUT31 / SYSCLK IN52 / OUT52 line of GPTA IN53 / OUT53 line of GPTA IN54 / OUT54 line of GPTA IN55 / OUT55 line of GPTA System Clock Output
Data Sheet
15
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 2-2 Symbol Pin Definitions and Functions (cont'd) Pins I/O Pad Driver Class I/O A2 Power Functions Supply General Device Information
P5
VDDP
Port 5 Port 5 is a 16-bit bi-directional generalpurpose I/O port. In emulation, it is used as a trace port for OCDS Level 2 debug lines. In normal operation, it is used for GPTA I/O or the MLI0 interface. OCDSDBG0 IN40 / OUT40 OCDSDBG1 IN41 / OUT41 OCDSDBG2 IN42 / OUT42 OCDSDBG3 IN43 / OUT43 OCDSDBG4 IN44 / OUT44 OCDSDBG5 OCDS L2 Debug Line 0 (Pipeline Status Sig. PS0) line of GPTA OCDS L2 Debug Line 1 (Pipeline Status Sig. PS1) line of GPTA OCDS L2 Debug Line 2 (Pipeline Status Sig. PS2) line of GPTA OCDS L2 Debug Line 3 (Pipeline Status Sig. PS3) line of GPTA OCDS L2 Debug Line 4 (Pipeline Status Sig. PS4) line of GPTA OCDS L2 Debug Line 5 (Break Qualification Line BRK0) line of GPTA OCDS L2 Debug Line 6 (Break Qualification Line BRK1) line of GPTA OCDS L2 Debug Line 7 (Break Qualification Line BRK2) line of GPTA
P5.0
1
P5.1
2
P5.2
3
P5.3
4
P5.4
5
P5.5
6
P5.6
7
IN45 / OUT45 OCDSDBG6
P5.7
8
IN46 / OUT46 OCDSDBG7
IN47 / OUT47
Data Sheet
16
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 2-2 Symbol Pin Definitions and Functions (cont'd) Pins I/O Pad Driver Class 13 Power Functions Supply OCDSDBG8 RDATA0B P5.9 14 OCDSDBG9 RVALID0B P5.10 15 OCDSDBG10 RREADY0B P5.11 16 OCDSDBG11 RCLK0B P5.12 17 OCDSDBG12 TDATA0 P5.13 18 OCDSDBG13 TVALID0B P5.14 19 OCDSDBG14 TREADY0B P5.15 20 OCDSDBG15 TCLK0 OCDS L2 Debug Line 8 (Indirect PC Addr. PC0) MLI0 receive channel data input B OCDS L2 Debug Line 9 (Indirect PC Addr. PC1) MLI0 receive channel valid input B OCDS L2 Debug Line 10 (Indirect PC Addr. PC2) MLI0 receive channel ready output B OCDS L2 Debug Line 11 (Indirect PC Addr. PC3) MLI0 receive channel clock input B OCDS L2 Debug Line 12 (Indirect PC Addr. PC04) MLI0 transmit channel data output B OCDS L2 Debug Line 13 (Indirect PC Addr. PC05) MLI0 transmit channel valid output B OCDS L2 Debug Line 14 (Indirect PC Address PC6) MLI0 transmit channel ready input B OCDS L2 Debug Line 15 (Indirect PC Address PC7) MLI0 transmit channel clock output B General Device Information
P5.8
Data Sheet
17
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 2-2 Symbol Pin Definitions and Functions (cont'd) Pins I/O Pad Driver Class C FCLP0A 157 FCLN0 SOP0A SON0 156 159 158 O O O O Power Functions Supply General Device Information
MSC0 Outputs
VDDP
LVDS MSC Clock and Data Outputs4) MSC0 Differential Driver Clock Output Positive A MSC0 Differential Driver Clock Output Negative MSC0 Differential Driver Serial Data Output Positive A MSC0 Differential Driver Serial Data Output Negative
Data Sheet
18
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 2-2 Symbol Pin Definitions and Functions (cont'd) Pins I/O Pad Driver Class I D Power Functions Supply General Device Information
Analog Inputs AN[35:0] - Analog Input Port The Analog Input Port provides altogether 36 analog input lines to ADC0 and FADC. AN[31:0]: ADC0 analog inputs [31:0] AN[35:32]: FADC analog differential inputs Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 Analog input 8 Analog input 9 Analog input 10 Analog input 11 Analog input 12 Analog input 13 Analog input 14 Analog input 15 Analog input 16 Analog input 17 Analog input 18 Analog input 19 Analog input 20 Analog input 21 Analog input 22 Analog input 23 Analog input 24 Analog input 25 Analog input 26 Analog input 27 Analog input 28 Analog input 29 Analog input 30
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30
67 66 65 64 63 62 61 36 60 59 58 57 56 55 50 49 48 47 46 45 44 43 42 41 40 39 38 37 35 34 33
Data Sheet
19
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 2-2 Symbol Pin Definitions and Functions (cont'd) Pins I/O Pad Driver Class 32 31 30 29 28 114 115 111 113 112 117 116 9 120 122 121 I D Power Functions Supply - Analog input 31 Analog input 32 Analog input 33 Analog input 34 Analog input 35 JTAG Module Reset/Enable Input JTAG Module Clock Input JTAG Module Serial Data Input JTAG Module Serial Data Output JTAG Module State Machine Control Input OCDS Break Input (Alternate Output)4)5) OCDS Break Output (Alternate Input)4)5) Trace Clock for OCDS_L2 Lines4) Non-Maskable Interrupt Input Hardware Reset Input / Reset Indication Output Power-on Reset Input PLL Clock Bypass Select Input This input has to be held stable during poweron resets. With BYPASS = 1, the spike filters in the HDRST, PORST and NMI inputs are switched off. Test Mode Select Input For normal operation of the TC1163/TC1164, this pin should be connected to high level. Input/Output Pins General Device Information
AN31 AN32 AN33 AN34 AN35 TRST TCK TDI TDO TMS BRKIN BRK OUT TRCLK NMI HDRST PORST
9)
System I/O I I I O I A23) A23) A13) A2 A2
3)
I/O A3 I/O A3 O I A4 A26)7)
VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP VDDP
I/O A28) I I A26)7) A13)
BYPASS 119
TEST MODE XTAL1 XTAL2
118
I
A26)10)
VDDP
102 103
I O
n.a.
VDDOSC Oscillator/PLL/Clock Generator
Data Sheet
20
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 2-2 Symbol Pin Definitions and Functions (cont'd) Pins I/O Pad Driver Class 21, 89 - - Power Functions Supply - Not Connected These pins are reserved for future extension and must not be connected externally. General Device Information
N.C.
Power Supplies
VDDM VSSM VDDMF VSSMF VDDAF VSSAF VAREF0 VAGND0 VFAREF VFAGND VDDOSC VDDOSC3 VSSOSC VDDFL3 VDD
54 53 24 25 23 22 52 51 26 27 105 106 104 141
- - - - - - - - - - - - - -
- - - - - - - - - - - - - - -
- - - - - - - - - - - - - - -
ADC Analog Part Power Supply (3.3 V) ADC Analog Part Ground for VDDM FADC Analog Part Power Supply (3.3 V) FADC Analog Part Ground for VDDMF FADC Analog Part Logic Power Supply (1.5 V) FADC Analog Part Logic Ground for VDDAF ADC Reference Voltage ADC Reference Ground FADC Reference Voltage FADC Reference Ground Main Oscillator and PLL Power Supply (1.5 V) Main Oscillator Power Supply (3.3 V) Main Oscillator and PLL Ground Power Supply for Flash (3.3 V) Core Power Supply (1.5 V)
10, - 68, 84, 99, 123, 153, 170
Data Sheet
21
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 2-2 Symbol Pin Definitions and Functions (cont'd) Pins I/O Pad Driver Class 11, - 69, 83, 100, 124, 154, 171, 139 12, - 70, 85, 101, 125, 155, 172, 140, 82 - Power Functions Supply - Port Power Supply (3.3 V) General Device Information
VDDP
VSS
-
-
Ground
1) Not applicable to TC1163 2) The logical AND function of the two slave select outputs is available as a third alternate output function. 3) These pads are I/O pads with input only function. Its input characteristics are identical with the input characteristics as defined for class A pads. 4) In case of a power-fail condition (one or more power supply voltages drop below the specified voltage range), an undefined output driving level may occur at these pins. 5) Programmed by software as either break input or break output. 6) These pads are input only pads with input characteristics. 7) Input only pads with input spike filter. 8) Open drain pad with input spike filter. 9) The dual input reset system of TC1163/TC1164 assumes that the PORST reset pin is used for power on reset only. 10) Input only pads without input spike filter.
Data Sheet
22
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 2-3 Pins All GPIOs, TDI, TMS, TDO HDRST BYPASS TRST, TCK TRCLK NMI, PORST General Device Information List of Pull-up/Pull-down Reset Behavior of the Pins PORST = 0 Pull-up Drive-low Pull-up High-impedance High-impedance Pull-down Pull-up High-impedance Pull-down PORST = 1
BRKIN, BRKOUT, TESTMODE Pull-up
Data Sheet
23
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3
Functional Description
Chapter 3 provides an overview of the TC1163/TC1164 functional description.
3.1
System Architecture and On-Chip Bus Systems
The TC1163/TC1164 has two independent on-chip buses (see also TC1163/TC1164 block diagram on Page 2-6): * * Local Memory Bus (LMB) System Peripheral Bus (SPB)
The LMB Bus connects the CPU local resources for data and instruction fetch. The Local Memory Bus interconnects the memory units and functional units, such as CPU and PMU. The main target of the LMB bus is to support devices with fast response times, optimized for speed. This allows the DMI and PMI fast access to local memory and reduces load on the FPI bus. The Tricore system itself is located on LMB bus. The Local Memory Bus is a synchronous, pipelined, split bus with variable block size transfer support. It supports 8-, 16-, 32- and 64-bit single transactions and variable length 64-bit block transfers. The SPB Bus is mainly governed by the PCP and is accessible to the CPU via the LMB Bus bridge. The System Peripheral Bus (SPB Bus) in TC1163/TC1164 is an on-chip FPI Bus. The FPI Bus interconnects the functional units of the TC1163/TC1164, such as the DMA and on-chip peripheral components. The FPI Bus is designed to be quick to be acquired by on-chip functional units, and quick to transfer data. The low setup overhead of the FPI Bus access protocol guarantees fast FPI Bus acquisition, which is required for time-critical applications.The FPI Bus is designed to sustain high transfer rates. For example, a peak transfer rate of up to 320 Mbyte/s can be achieved with a 80 MHz bus clock and 32-bit data bus. Multiple data transfers per bus arbitration cycle allow the FPI Bus to operate at close to its peak bandwidth. Both the LMB Bus and the SPB Bus runs at full CPU speed. The maximum CPU speed is 80 MHz. Additionally, two simplified bus interfaces are connected to and controlled by the DMA Controller: * * DMA Bus SMIF Interface
Data Sheet
24
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.2
On-Chip Memories
As shown in the TC1163/TC1164 block diagram on Page 2-6, some of the TC1163/TC1164 units provide on-chip memories that are used as program or data memory. * Program memory in PMU - 16 Kbyte Boot ROM (BROM) - 1024 Kbyte Program Flash (PFlash) Program memory in PMI - 8 Kbyte Scratch-Pad RAM (SPRAM) - 8 Kbyte Instruction Cache (ICACHE) Data memory in PMU - 16 Kbyte Data Flash (DFlash) - 8 Kbyte Overlay RAM (OVRAM) Data memory in DMI - 40 Kbyte Local Data RAM (LDRAM) Memory of PCP2 - 12 Kbyte Code Memory (CMEM) with parity error protection - 8 Kbyte Parameter RAM (PRAM) with parity error protection On-chip SRAM with parity error protection
*
*
* *
*
Features of Program Flash * * * * * * * 1024 Kbyte on-chip program Flash memory Usable for instruction code or constant data storage 256-byte program interface - 256 bytes are programmed into PFLASH page in one step/command 256-bit read interface - Transfer from PFLASH to CPU/PMI by four 64-bit single cycle burst transfers Dynamic correction of single-bit errors during read access Detection of double-bit errors Fixed sector architecture - Eight 16 Kbyte, one 128 Kbyte, one 256 Kbyte and one 512 Kbyte sectors - Each sector separately erasable - Each sector separately write-protectable Configurable read protection for complete PFLASH with sophisticated read access supervision, combined with write protection for complete PFLASH (protection against "Trojan horse" software) Configurable write protection for each sector - Each sector separately write-protectable - With capability to be re-programmed - With capability to be locked forever (OTP) Password mechanism for temporary disabling of write and read protection On-chip generation of programming voltage
25 V1.0, 2008-04
*
*
* *
Data Sheet
TC1163/TC1164
Preliminary * Functional Description
*
JEDEC-standard based command sequences for PFLASH control - Write state machine controls programming and erase operations - Status and error reporting by status flags and interrupt Margin check for detection of problematic PFLASH bits
Features of Data Flash * * * * * * * 16 Kbyte on-chip data Flash memory, organized in two 8 Kbyte banks Usable for data storage with EEPROM functionality 128 Byte of program interface - 128 bytes are programmed into one DFLASH page by one step/command 64-bit read interface (no burst transfers) Dynamic correction of single-bit errors during read access Detection of double-bit errors Fixed sector architecture - Two 8 Kbyte banks/sectors - Each sector separately erasable Configurable read protection (combined with write protection) for complete DFLASH together with PFLASH read protection Password mechanism for temporary disabling of write and read protection Erasing/programming of one bank possible while reading data from the other bank Programming of one bank while erasing the other bank possible On-chip generation of programming voltage JEDEC-standard based command sequences for DFLASH control - Write state machine controls programming and erase operations - Status and error reporting by status flags and interrupt Margin check for detection of problematic DFLASH bits
* * * * * *
*
Data Sheet
26
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.3
Memory Maps
This chapter gives an overview of the TC1163/TC1164 memory map and describes the address locations and access possibilities for the units, memories, and reserved areas as "seen" from different on-chip buses' (SPB and LMB) point of view.
3.3.1
Architectural Address Map
Table 3-1 shows the overall architectural address map as defined for the TriCore and as implemented in TC1163/TC1164. Table 3-1 Segment 0-7 8 9 10 11 12 13 TC1163/TC1164 Architectural Address Map Size 8 x 256 Mbyte 256 Mbyte 256 Mbyte 256 Mbyte 256 Mbyte 256 Mbyte 64 Mbyte 64 Mbyte 96 Mbyte 16 Mbyte 16 Mbyte Description Reserved (MMU space); cached Reserved (246 Mbyte); PMU, Boot ROM; cached FPI space; cached Reserved (246 Mbyte), PMU, Boot ROM; noncached FPI space; non-cached Reserved; bottom 4 Mbyte visible from FPI bus in segment 14; cached Local Data Memory RAM; non-cached Local Code Memory RAM; non-cached Reserved; non-cached Reserved; non-cached Boot ROM space, Boot ROM mirror; non-cached
Contents Global Global Memory Global Memory Global Memory Global Memory Local LMB Memory DMI PMI EXT_PER EXT_EMU BOOTROM
Data Sheet
27
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 3-1 Segment 14 Functional Description TC1163/TC1164 Architectural Address Map (cont'd) Size 128 Mbyte 16 x 8 Mbyte 256 Mbyte Description Reserved; non-speculative; non-cached; no execution Non-speculative; non-cached; no execution CSFRs of CPUs[0 ..15]; LMB & FPI Peripheral Space; non-speculative; non-cached; no execution
Contents EXTPER CPU[0 ..15] image region
15
LMB_PER CSFRs INT_PER
Data Sheet
28
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.3.2
How to Read the Address Maps
The bus-specific address maps describe how the different bus master devices react on accesses to on-chip memories and modules, and which address ranges are valid or invalid for the corresponding buses. The FPI Bus address map shows the system addresses from the point of view of the SPB master agents. SPB master agents are PCP2 and OCDS, and DMA. The LMB address map shows the system addresses from the point of view of the LMB master agents. LMB master agents are PMI and DMI. Table 3-2 defines the acronyms and other terms that are used in the address maps (Table 3-3 to Table 3-5). Table 3-2 Term ...BE ...BET SPBBE SPBBET LMBBE LMBBET access ignore trap 32 nE Definition of Acronyms and Terms Description Means "Bus error" generation. Means "Bus error & trap" generation. A bus access is terminated with a bus error on the SPB. A bus access is terminated with a bus error on the SPB and a DSE trap (read access) or DAE trap (write access). A bus access is terminated with a bus error on the LMB. A bus access is terminated with a bus error on the LMB and a DSE trap (read access) or DAE trap (write access). A bus access is allowed and is executed. A bus access is ignored and is not executed. No bus error is generated. A DSE trap (read access) or DAE trap (write access) is generated. Only 32-bit word bus accesses are permitted to that register/address range. A bus access generates no bus error, although the bus access points to an undefined address or address range. This is valid e.g. for CPU accesses (MTCR/MFCR) to undefined addresses in the CSFR range.
Data Sheet
29
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.3.3
Contents of the Segments
This section summarizes the contents of the segments. Segments 0-7 These segments are reserved segments in the TC1163/TC1164. Segment 8 From the SPB point of view (PCP, DMA and Cerberus), this memory segment allows accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM). From the CPU point of view (PMI and DMI), this memory segment allows cached accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM). Segment 9 This memory segment is reserved in the TC1163/TC1164. Segment 10 From the SPB point of view (PCP, DMA and Cerberus), this memory segment allows accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM). From the CPU point of view (PMI and DMI), this memory segment allows non-cached accesses to all PMU memories (PFLASH, DFLASH, BROM, and TROM). Segment 11 This memory segment is reserved in the TC1163/TC1164. Segment 12 From the SPB point of view (PCP, DMA, and Cerberus), this memory segment is reserved in the TC1163/TC1164. From the CPU point of view (PMI and DMI), this memory segment allows cached accesses to the PMU memory, OVRAM. Segment 13 From the SPB point of view (PCP, DMA and Cerberus), this memory segment is reserved in the TC1163/TC1164. From the CPU point of view (PMI and DMI), this memory segment allows non-cached accesses to the PMI scratch-pad RAM, read access to the boot ROM and test ROM (BROM and TROM) and the DMI memories (LDRAM).
Data Sheet
30
V1.0, 2008-04
TC1163/TC1164
Preliminary Segment 14 From the SPB point of view (PCP, DMA and Cerberus), this memory segment allows accesses to the PMU Overlay memory (OVRAM), the DMI Local Data RAM (LDRAM), and the PMI scratch-pad RAM (SPRAM). From the CPU point of view (PMI and DMI), this memory segment is reserved in the TC1163/TC1164. Segment 15 From the SPB point of view (PCP, DMA and Cerberus), this memory segment allows accesses to all SFRs and CSFRs, the PCP memories, and the MLI transfer windows. From the CPU point of view (PMI and DMI), this memory segment allows accesses to all SFRs and CSFRs, the PCP memories, and the MLI transfer windows. Functional Description
Data Sheet
31
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TC1163/TC1164
Preliminary Functional Description
3.3.4
Address Map of the FPI Bus System
Table 3-3 and Table 3-4 shows the address maps of the FPI Bus System.
3.3.4.1
Segments 0 to 14
Table 3-3 shows the address maps of segments 0 to 14 as it is seen from the SPB bus masters PCP, DMA and OCDS. Table 3-3 SPB Address Map of Segment 0 to 14 Size 8 byte 8 x 256 Mbyte Description Reserved (virtual address space) Access Type Read MPN trap SPBBE Write MPN trap SPBBE
Seg- Address ment Range 0-7 0000 0000H 0000 0007H 0000 0008H 7FFF FFFFH
Data Sheet
32
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 3-3 Functional Description SPB Address Map of Segment 0 to 14 (cont'd) Size 1 Mbyte 0.5 Mbyte Description Program Flash (PFLASH) Reserved Access Type Read access access2) LMBBE & SPBBE LMBBE & SPBBE access access2) LMBBE & SPBBE access access2) LMBBE & SPBBE Write access1) access1)2) LMBBE LMBBE access1) access1)2) LMBBE access1) access1)2) LMBBE
Seg- Address ment Range 8 8000 0000H 800F FFFFH 8010 0000H 8017 7FFFH 8017 8000H 807F FFFFH 8080 0000H 8FDF FFFFH 8FE0 0000H 8FE0 1FFFH 8FE0 2000H 8FE0 3FFFH 8FE0 4000H 8FE0 FFFFH 8FE1 0000H 8FE1 1FFFH 8FE1 2000H 8FE1 3FFFH 8FE1 4000H 8FF1 FFFFH 8FF2 0000H 8FF5 FFFFH 8FF6 0000H 8FFF BFFFH
6.5 Mbyte Reserved 246 Mbyte 8 Kbyte 8 Kbyte 48 Kbyte 8 Kbyte 8 Kbyte 1 Mbyte 256 Kbyte 624 Kbyte Reserved Data Flash (DFLASH) Bank 0 Reserved Reserved Data Flash (DFLASH) Bank 1 Reserved Reserved Reserved Reserved Boot ROM (BROM) Reserved
8FFF C000H - 16 Kbyte 8FFF FFFFH 9 9000 0000H 9FFF FFFFH 256 Mbyte
access SPBBE SPBBE
Data Sheet
33
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 3-3 Functional Description SPB Address Map of Segment 0 to 14 (cont'd) Size 1 Mbyte 0.5 Mbyte Description Program Flash (PFLASH) Reserved Access Type Read access access2) LMBBE & SPBBE LMBBE & SPBBE access access2) LMBBE & SPBBE access access2) LMBBE & SPBBE Write access1) access1)2) LMBBE LMBBE access1) access1)2) LMBBE access1) access1)2) ignore
Seg- Address ment Range 10 A000 0000H A00F FFFFH A010 0000H A017 FFFFH A017 8000H A07F FFFFH A080 0000H AFDF FFFFH AFE0 0000H AFE0 1FFFH AFE0 2000H AFE0 3FFFH AFE0 4000H AFE0 FFFFH AFE1 0000H AFE1 1FFFH AFE1 2000H AFE1 3FFFH AFE1 4000H AFF1 FFFFH AFF2 0000H AFF5 FFFFH AFF6 0000H AFFF BFFFH
6.5 Mbyte Reserved 246 Mbyte 8 Kbyte 8 Kbyte 48 Kbyte 8 Kbyte 8 Kbyte 1 Mbyte 256 Kbyte 624 Kbyte Reserved Data Flash (DFLASH) Bank 0 Reserved Reserved Data Flash (DFLASH) Bank 1 Reserved Reserved Reserved Reserved Boot ROM (BROM) Reserved Overlay memory (OVRAM) Reserved
AFFF C000H - 16 Kbyte AFFF FFFFH 11 12 B000 0000H BFFF FFFFH C000 0000H C000 1FFFH C000 2000H CFFF FFFFH 256 Mbyte 8 Kbyte 256 Mbyte
access SPBBE SPBBE SPBBE SPBBE SPBBE SPBBE
Data Sheet
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Preliminary Table 3-3 Functional Description SPB Address Map of Segment 0 to 14 (cont'd) Size 40 Kbyte 64 Mbyte 8 Kbyte 64 Mbyte 112 Mbyte 16 Mbyte Description DMI Local Data RAM (LDRAM) Reserved PMI Scratch-Pad RAM (SPRAM) Reserved Reserved Reserved (for Boot Rom) microROM Access Type Read SPBBE SPBBE SPBBE SPBBE SPBBE SPBBE SPBBE Write SPBBE SPBBE SPBBE SPBBE SPBBE SPBBE SPBBE
Seg- Address ment Range 13 D000 0000H D000 9FFFH D000 A000H D3FF FFFFH D400 0000H D400 1FFFH D400 2000H D7FF FFFFH D800 0000H DEFF FFFFH DF00 0000H DFFF FFEFH
DFFF FFF0H - 16 byte DFFF FFFFH
Data Sheet
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Preliminary Table 3-3 Functional Description SPB Address Map of Segment 0 to 14 (cont'd) Size 128 MB 8 Kbyte 4 Mbyte 40 Kbyte 16 Kbyte Description Reserved Overlay memory (OVRAM) Reserved DMI Local Data RAM (LDRAM) Reserved Access Type Read LMBBE access LMBBE access access2) LMBBE access access2) LMBBE LMBBE Write LMBBE access LMBBE access access2) LMBBE access access2) LMBBE LMBBE
Seg- Address ment Range 14 E000 0000H E7FF FFFFH E800 0000H E800 1FFFH E800 2000H E83F FFFFH E840 0000H E840 9FFFH E840 A000H E840 DFFFH E840 E000H E84F FFFFH E850 0000H E850 1FFFH E850 2000H E850 3FFFH E850 4000H E85F FFFFH E860 C000H EFFF FFFFH 15 F000 0000H FFFF FFFFH
1 Mbyte Reserved 8 Kbyte 8 Kbyte PMI Scratch-Pad RAM (SPRAM) Reserved
1 Mbyte Reserved 122 Mbyte 256 Mbyte Reserved see Table 3-4
1) Only applicable when writing Flash command sequences. 2) Read and write accesses to this address range will not generate any traps.
Data Sheet
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Preliminary Functional Description
3.3.4.2
Segment 15
Table 3-4 shows the address map of segment 15 as seen from the SPB bus masters PCP, DMA and OCDS. Please note that access in Table 3-4 means only that an access to an address within the defined address range is not automatically incorrect or ignored. If an access is really addressing a correct address, it can be found in the detailed tables in the TC116x User's Manual, Register Overview's chapter. Table 3-4 Unit System Control Unit (SCU) and Watchdog Timer (WDT) SPB Address Map of Segment 15 Address Range F000 0000H F000 00FFH Size 256 byte 256 byte 256 byte - 256 byte - 256 byte - 256 byte 256 byte 256 byte 256 byte 256 byte Access Type Read access access access SPBBE access SPBBE access SPBBE access access access access access Write access access access SPBBE access SPBBE access SPBBE access access access access access
System Peripheral Bus Control Unit F000 0100H (SBCU) F000 01FFH System Timer (STM) Reserved F000 0200H F000 02FFH F000 0300H F000 03FFH
On-Chip Debug Support (Cerberus) F000 0400H F000 04FFH Reserved MicroSecond Bus Controller 0 (MSC0) Reserved Async./Sync. Serial Interface 0 (ASC0) Async./Sync. Serial Interface 1 (ASC1) Port 0 Port 1 Port 2 F000 0500H F000 07FFH F000 0800H F000 08FFH F000 0900H F000 09FFH F000 0A00H F000 0AFFH F000 0B00H F000 0BFFH F000 0C00H F000 0CFFH F000 0D00H F000 0DFFH F000 0E00H F000 0EFFH
Data Sheet
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Preliminary Table 3-4 Unit Port 3 Port 4 Port 5 Reserved Reserved Reserved Reserved Reserved Reserved General Purpose Timer Array 0 (GPTA0) Reserved Reserved Reserved Direct Memory Access Controller (DMA) Reserved MultiCAN Controller (CAN) SPB Address Map of Segment 15 (cont'd) Address Range F000 0F00H F000 0FFFH F000 1000H F000 10FFH F000 1100H F000 11FFH F000 1200H F000 12FFH F000 1300H F000 13FFH F000 1400H F000 14FFH F000 1500H F000 15FFH F000 1600H F000 16FFH F000 1700H F000 17FFH F000 1800H F000 1FFFH F000 2000H F000 27FFH F000 2800H F000 2FFFH F000 3000H F000 3BFFH F000 3C00H F000 3EFFH F000 3F00H F000 3FFFH F000 4000H F000 5FFFH Size 256 byte 256 byte 256 byte - - - - - - 8 x 256 byte - - - 3 x 256 byte - Access Type Read access access access SPBBE SPBBE SPBBE SPBBE SPBBE SPBBE access SPBBE SPBBE SPBBE access SPBBE Write access access access SPBBE SPBBE SPBBE SPBBE SPBBE SPBBE access SPBBE SPBBE SPBBE access SPBBE access1) Functional Description
8 Kbyte access1)
Data Sheet
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Preliminary Table 3-4 Unit Reserved Reserved PCP Registers Reserved PCP Data Memory (PRAM) Reserved PCP Code Memory (PCODE) Reserved Reserved Reserved Synchronous Serial Interface 0 (SSC0) Synchronous Serial Interface 1 (SSC1) Fast Analog-to-Digital Converter (FADC) Analog-to-Digital Converter 0 (ADC0) Reserved Reserved SPB Address Map of Segment 15 (cont'd) Address Range F000 6000H F003 FFFFH F004 0000H F004 3EFFH F004 3F00H F004 3FFFH F004 4000H F004 FFFFH F005 0000H F005 1FFFH F005 2000H F005 FFFFH F006 0000H F006 2FFFH F006 3000H F007 FFFFH F008 0000H F00F FFFFH F010 0000H F010 00FFH F010 0100H F010 01FFH F010 0200H F010 02FFH F010 0300H F010 03FFH F010 0400H F010 05FFH F010 0600H F010 07FFH F010 0800H F010 9FFFH Size - - 256 byte - Access Type Read SPBBE SPBBE access SPBBE Write SPBBE SPBBE access SPBBE nE, 32 SPBBE nE, 32 SPBBE SPBBE SPBBE access access access access SPBBE SPBBE Functional Description
8 Kbyte nE, 32 - 12 Kbyte - - - 256 byte 256 byte 256 byte 2 x 256 byte - - SPBBE nE, 32 SPBBE SPBBE SPBBE access access access access SPBBE SPBBE
Data Sheet
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Preliminary Table 3-4 Unit Reserved Micro Link Interface 0 (MLI0) Reserved Memory Checker (MCHK) Reserved MLI0 Small Transfer Windows Reserved Reserved MLI0 Large Transfer Windows Reserved Reserved CPU CPU Slave Interface Registers (CPS) CPU Core SFRs & GPRs Reserved Reserved Reserved SPB Address Map of Segment 15 (cont'd) Address Range F010 A000H F010 BFFFH F010 C000H F010 C0FFH F010 C100H F010 C1FFH F010 C200H F010 C2FFH F010 C300H F01D FFFFH F01E 0000H F01E 7FFFH F01E 8000H F01E FFFFH F01F 0000H F01F FFFFH F020 0000H F023FFFFH F024 0000H F027 FFFFH F028 0000H F7E0 FEFFH F7E0 FF00H F7E0 FFFFH F7E1 0000H F7E1 FFFFH F7E2 0000H F7FF FFFFH F800 0000H F800 03FFH F800 0400H F800 04FFH Size - 256 byte 256 byte 256 byte - 4x8 Kbyte 4x8 Kbyte - 4 x 64 Kbyte 4 x 64 Kbyte - 256 byte 64 Kbyte - - - Access Type Read SPBBE access access2) access SPBBE access access2) SPBBE access access2) SPBBE access access SPBBE SPBBE LMBBE & SPBBE Write SPBBE access access2) access SPBBE access access2) SPBBE access access2) SPBBE access access SPBBE SPBBE LMBBE Functional Description
Data Sheet
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Preliminary Table 3-4 Unit Program Memory Unit (PMU) Reserved Flash Register Reserved Reserved Reserved Reserved Reserved CPU DMI Registers PMI Registers Local Memory Bus Control Unit (LBCU) LFI Bridge Reserved SPB Address Map of Segment 15 (cont'd) Address Range F800 0500H F800 05FFH F800 0600H F800 0FFFH F800 1000H F800 23FFH F800 2400H F801 00FFH F801 0100H F801 01FFH F801 0200H F87F F9FFH F87F FA00H F87F FAFFH F87F FB00H F87F FBFFH Size 256 byte - Access Type Read access LMBBE & SPBBE Write access LMBBE access LMBBE LMBBE LMBBE LMBBE LMBBE access access access access LMBBE Functional Description
5 Kbyte access - - - - - LMBBE & SPBBE LMBBE & SPBBE LMBBE & SPBBE LMBBE & SPBBE LMBBE & SPBBE access access access access LMBBE & SPBBE
F87F FC00H - 256 F87F FCFFH byte F87F FD00H - 256 F87F FDFFH byte F87F FE00H F87F FEFFH F87F FF00H F87F FFFFH F880 0000H FFFF FFFFH 256 byte 256 byte -
1) For TC1163, read and write accesses to this address range will not generate any traps. 2) Read and write accesses to this address range will not generate any traps.
Data Sheet
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Preliminary Functional Description
3.3.5
Address Map of the Local Memory Bus (LMB)
Table 3-5 shows the address map as seen from the LMB bus masters (PMI and DMI). Table 3-5 LMB Address Map Size 8 byte 8 x 256 Mbyte 1 Mbyte 0.5 Mbyte Description Read Reserved (virtual address MPN trap space) SPBBET Program Flash (PFLASH) access Reserved access3) LMBBET LMBBET access access3) LMBBET access access3) LMBBET Action Write MPN trap SPBBE access2) access2)3) LMBBET LMBBET access2) access2)3) LMBBET access2) access2)3) LMBBET
Seg- Address ment Range 0-71) 0000 0000H 0000 0007H 0000 0008H 7FFF FFFFH 81) 8000 0000H 800F FFFFH 8010 0000H 8017 7FFFH 8017 8000H 807F FFFFH 8080 0000H 8FDF FFFFH 8FE0 0000H 8FE0 1FFFH 8FE0 2000H 8FE0 3FFFH 8FE0 4000H 8FE0 FFFFH 8FE1 0000H 8FE1 1FFFH 8FE1 2000H 8FE1 3FFFH 8FE1 4000H 8FF1 FFFFH 8FF2 0000H 8FF5 FFFFH 8FF6 0000H 8FFF BFFFH
6.5 Mbyte Reserved 246 Mbyte 8 Kbyte 8 Kbyte 48 Kbyte 8 Kbyte 8 Kbyte 1 Mbyte Reserved Data Flash (DFLASH) Bank 0 Reserved Reserved Data Flash (DFLASH) Bank 1 Reserved Reserved
256 Kbyte Reserved 624 Kbyte Reserved Boot ROM (BROM) access
8FFF C000H - 16 Kbyte 8FFF FFFFH
Data Sheet
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Preliminary Table 3-5 LMB Address Map (cont'd) Size 256 Mbyte 1 Mbyte 0.5 Mbyte Description Read Reserved SPBBET Action Write SPBBE access2) access2)3) LMBBET LMBBET access2) access2)3) LMBBET access2) access2)3) LMBBET Functional Description
Seg- Address ment Range 9
1)
9000 0000H 9FFF FFFFH A000 0000H A00F FFFFH A010 0000H A017 FFFFH A017 8000H A07F FFFFH A080 0000H AFDF FFFFH AFE0 0000H AFE0 1FFFH AFE0 2000H AFE0 3FFFH AFE0 4000H AFE0 FFFFH AFE1 0000H AFE1 1FFFH AFE1 2000H AFE1 3FFFH AFE1 4000H AFF1 FFFFH AFF2 0000H AFF5 FFFFH AFF6 0000H AFFF BFFFH
104)
Program Flash (PFLASH) access Reserved access3) LMBBET LMBBET access access3) LMBBET access access3) LMBBET
6.5 Mbyte Reserved 246 Mbyte 8 Kbyte 8 Kbyte 48 Kbyte 8 Kbyte 8 Kbyte 1 Mbyte Reserved Data Flash (DFLASH) Bank 0 Reserved Reserved Data Flash (DFLASH) Bank 1 Reserved Reserved
256 Kbyte Reserved 624 Kbyte Reserved Boot ROM (BROM) Reserved access SPBBET SPBBE
AFFF C000H - 16 Kbyte AFFF FFFFH 114) B000 0000H BFFF FFFFH 256 Mbyte
Data Sheet
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Preliminary Table 3-5 LMB Address Map (cont'd) Size 8 Kbyte 256 Mbyte 40 Kbyte 16 Kbyte 64 Mbyte 8 Kbyte 8 Kbyte 64 Mbyte 112 Mbyte 16 Mbyte 128 Mbyte 128 Mbyte Description Read Overlay memory (OVRAM) Reserved DMI Local Data RAM (LDRAM) Reserved Reserved PMI Scratch-Pad RAM (SPRAM) Reserved Reserved Reserved Reserved (for Boot Rom) Reserved Reserved LMBBET LMBBET LMBBET LMBBET access LMBBET access SPBBE access SPBBE5) LMBBET access access3) LMBBET Action Write access LMBBET access SPBBE access SPBBE5) LMBBET access access3) LMBBET Functional Description
Seg- Address ment Range 12
1)
C000 0000H C000 1FFFH C000 2000H CFFF FFFFH
134)
D000 0000H D000 9FFFH D000 A000H D000 DFFFH D000 E000H D3FF FFFFH D400 0000H D400 1FFFH D400 2000H D400 3FFFH D400 4000H D7FF FFFFH D800 0000H DEFF FFFFH DF00 0000H DFFF FFEFH
144)
E000 0000H E7FF FFFFH E800 0000H EFFF FFFFH
Data Sheet
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Preliminary Table 3-5 LMB Address Map (cont'd) Size 128 Mbyte Description Read Address map is identical to FPI Bus segment 15 address map (see Table 3-5) Reserved areas give an bus error. Reserved Reserved Program Memory Unit (PMU) SPBBET Action Write SPBBE Functional Description
Seg- Address ment Range 15 F000 0000H F7FF FFFFH
F800 0000H F800 03FFH F800 0400H F800 04FFH F800 0500H F800 05FFH F800 0600H F800 0FFFH F800 1000H F800 23FFH F800 2400H F87F FBFFH
1 Kbyte 256 byte 256 byte
LMBBET LMBBET access LMBBET access LMBBET access access access access LMBBET
LMBBET LMBBET access LMBBET access LMBBET access access access access LMBBET
2 Kbyte Reserved 5 Kbyte Flash Registers
8 Mbyte Reserved Data Memory Interface Unit Program Memory Interface Unit LBCU register space LFI Bus Bridge Reserved
F87F FC00H - 256 byte F87F FCFFH F87F FD00H - 256 byte F87F FDFFH F87F FE00H - 256 byte F87F FEFFH F87F FF00H F87F FFFFH F880 0000H FFFF FFFFH
1) Cached area
256 byte 119 Mbyte
2) Only applicable when writing Flash command sequences 3) Read and write accesses to this address range will not generate any traps. 4) Non-cached area 5) If accessible, read and write accesses to this address range will not generate any traps.
Data Sheet
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Preliminary Functional Description
3.4
Memory Protection System
The TC1163/TC1164 memory protection system specifies the addressable range and read/write permissions of memory segments available to the current executing task. The memory protection system controls the position and range of addressable segments in memory. It also controls the types of read and write operations allowed within addressable memory segments. Any illegal memory access is detected by the memory protection hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the error. Thus, the memory protection system protects critical system functions against both software and hardware errors. The memory protection hardware can also generate signals to the Debug Unit to facilitate tracing illegal memory accesses. There are two Memory Protection Register Sets in the TC1163/TC1164, numbered 0 and 1, which specify memory protection ranges and permissions for code and data. The PSW.PRS bit field determines which of these is the set currently in use by the CPU. As the TC1163/TC1164 uses a Harvard-style memory architecture, each Memory Protection Register Set is broken down into a Data Protection Register Set and a Code Protection Register Set. Each Data Protection Register Set can specify up to four address ranges to receive a particular protection modes. Each Code Protection Register Set can specify up to two address ranges to receive a particular protection modes. Each Data Protection Register Sets and Code Protection Register Sets determines the range and protection modes for a separate memory area. Each set contains a pair of registers which determine the address range (the Data Segment Protection Registers and Code Segment Protection Registers) and one register (Data Protection Mode Register) which determines the memory access modes that applies to the specified range.
3.5
Peripheral Control Processor
The Peripheral Control Processor (PCP2) in the TC1163/TC1164 performs tasks that would normally be performed by the combination of a DMA controller and its supporting CPU interrupt service routines in a traditional computer system. It could easily be considered as the host processor's first line of defence as an interrupt-handling engine. The PCP can unload the CPU from having to service time-critical interrupts. This provides many benefits, including: * * * * Avoiding large interrupt-driven task context-switching latencies in the host processor Reducing the cost of interrupts in terms of processor register and memory overhead Improving the responsiveness of interrupt service routines to data-capture and datatransfer operations Easing the implementation of multitasking operating systems
The PCP2 has an architecture that efficiently supports DMA-type transactions to and from arbitrary devices and memory addresses within the TC1163/TC1164 and also has reasonable stand-alone computational capabilities.
Data Sheet
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Preliminary Functional Description
The PCP2 in the TC1163/TC1164 contains an improved version of the TC1775's PCP with the following enhancements: * * * * * * * * * * * Optimized context switching Support for nested interrupts Enhanced instruction set Enhanced instruction execution speed Enhanced interrupt queueing PCP Processor Core Code Memory (CMEM) Parameter Memory (PRAM) PCP Interrupt Control Unit (PICU) PCP Service Request Nodes (PSRN) System bus interface to the Flexible Peripheral Interface (FPI Bus)
The PCP2 is made up of several modular blocks as follows (see Figure 3-1):
Code Memory CMEM
Parameter Memory PRAM
PCP Processor Core
FPI-Interface
PCP Service Req. Nodes PSRNs
PCP Interrupt Control Unit PICU
FPI Bus
PCP Interrupt Arbitration Bus CPU Interrupt Arbitration Bus
MCB06135
Figure 3-1
PCP2 Block Diagram
Data Sheet
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Preliminary Table 3-6 PCP2 Instruction Set Overview Description Efficient DMA channel implementation Transfer data between PRAM or FPI memory and the general purpose registers, as well as move or exchange values between registers Add, subtract, compare and complement Divide and multiply And, Or, Exclusive Or, Negate Shift right or left, rotate right or left, prioritize Set, clear, insert and test bits Jump conditionally, jump long, exit No operation, Debug Functional Description
Instruction Group DMA primitives Load/Store
Arithmetic Divide/Multiply Logical Shift Bit Manipulation Flow Control Miscellaneous
Data Sheet
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Preliminary Functional Description
3.6
DMA Controller and Memory Checker
The DMA Controller of the TC1163/TC1164 transfers data from data source locations to data destination locations without intervention of the CPU or other on-chip devices. One data move operation is controlled by one DMA channel. Eight DMA channels are provided in one DMA Sub-Block. The Bus Switch provides the connection of the DMA Sub-Block to the two FPI Bus interfaces and an MLI bus interface. In the TC1163/TC1164, the FPI Bus interfaces are connected to the System Peripheral Bus and the DMA Bus. The third specific bus interface provides a connection to Micro Link Interface modules (two MLI modules in the TC1163/TC1164) and other DMA-related devices (Memory Checker module in the TC1163/TC1164). Clock control, address decoding, DMA request wiring, and DMA interrupt service request control are implementation-specific and managed outside the DMA controller kernel. Figure 3-2 shows the implementation details and interconnections of the DMA module.
Clock Control
f DMA
DMA Controller FPI Bus Interfac e 0
System Periphera Bus
DMA Sub-Block 0 DMA Requests of On-chip Periph. Units Request Selection/ CH0n_OUT Arbitration DMA Channels 00-07 Transaction Control Unit
Bus Switch
FPI Bus Interfac e 1
DMA Bus
MLI0 Address Decoder MLI Interface
Memory Checker
Interrupt Request Nodes
SR[15:0] DMA Interrupt Control
Arbiter/ Switch Control
TC1163/TC1164 DMA Block Diagram
Figure 3-2
DMA Controller Block Diagram
Data Sheet
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Preliminary Features * 8 independent DMA channels - 8 DMA channels in the DMA Sub-Block - Up to 8 selectable request inputs per DMA channel - 2-level programmable priority of DMA channels within the DMA Sub-Block - Software and hardware DMA request - Hardware requests by selected on-chip peripherals and external inputs Programmable priority of the DMA Sub-Blocks on the bus interfaces Buffer capability for move actions on the buses (at least 1 move per bus is buffered). Individually programmable operation modes for each DMA channel - Single Mode: stops and disables DMA channel after a predefined number of DMA transfers - Continuous Mode: DMA channel remains enabled after a predefined number of DMA transfers; DMA transaction can be repeated. - Programmable address modification Full 32-bit addressing capability of each DMA channel - 4 Gbyte address range - Support of circular buffer addressing mode Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit Micro Link bus interface support Register set for each DMA channel - Source and destination address register - Channel control and status register - Transfer count register Flexible interrupt generation (the service request node logic for the MLI channels is also implemented in the DMA module) All buses connected to the DMA module must work at the same frequency. Read/write requests of the System Bus side to the peripherals on DMA Bus are bridged to the DMA Bus (only the DMA is the master on the DMA bus), allowing easy access to these peripherals by PCP and CPU Functional Description
* * *
*
* * *
* * *
Memory Checker The Memory Checker Module (MCHK) makes it possible to check the data consistency of memories. Any SPB bus master may access the memory checker. It is preferable the DMA does it as described hereafter. It uses DMA 8-bit, 16-bit, or 32-bit moves to read from the selected address area and to write the value read in a memory checker input register. With each write operation to the memory checker input register, a polynomial checksum calculation is triggered and the result of the calculation is stored in the memory checker result register. The memory checker uses the standard Ethernet polynomial, which is given by: G32 = x32+ x26+ x23+ x22+ x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x +1
Data Sheet
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Preliminary Functional Description
Note: Although the polynomial above is used for generation, the generation algorithm differs from the one that is used by the Ethernet protocol.
3.7
Interrupt System
The TC1163/TC1164 interrupt system provides a flexible and time-efficient means of processing interrupts. An interrupt request can be serviced either by the CPU or by the Peripheral Control Processor (PCP). These units are called "Service Providers". Interrupt requests are called "Service Requests" rather than "Interrupt Requests" in this document because they can be serviced by either Service Providers. Each peripheral in the TC1163/TC1164 can generate service requests. Additionally, the Bus Control Units, the Debug Unit, the PCP, and even the CPU itself can generate service requests to either of the two Service Providers. As shown in Figure 3-3, each TC1163/TC1164 unit that can generate service requests is connected to one or multiple Service Request Nodes (SRN). Each SRN contains a Service Request Control Register mod_SRCx, where "mod" is the identifier of the service requesting unit and "x" an optional index. Two arbitration buses connect the SRNs with two Interrupt Control Units, which handle interrupt arbitration among competing interrupt service requests, as follows: * * The Interrupt Control Unit (ICU) arbitrates service requests for the CPU and administers the CPU Interrupt Arbitration Bus. The Peripheral Interrupt Control Unit (PICU) arbitrates service requests for the PCP and administers the PCP Interrupt Arbitration Bus.
The PCP can make service requests directly to itself (via the PICU), or it can make service requests to the CPU. The Debug Unit can generate service requests to the PCP or the CPU. The CPU can make service requests directly to itself (via the ICU), or it can make service requests to the PCP. The CPU Service Request Nodes are activated through software. Depending on the selected system clock frequency fSYS, the number of fSYS clock cycles per arbitration cycle must be selected as follows: * *
fSYS < 60 MHz: ICR.CONECYC = 1 and PCP_ICR.CONECYC = 1 fSYS > 60 MHz: ICR.CONECYC = 0 and PCP_ICR.CONECYC = 0
Data Sheet
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Preliminary Functional Description
PCP Interrupt Arbitration Bus Service Requestors Service Req. Nodes
CPU Interrupt Arbitration Bus PCP Interrupt Control Unit PICU Int. Req. Int. Ack. CCPN Interrupt Service Providers
MSC0 MLI0 SSC0 SSC1 ASC0 ASC1 MultiCAN1) ADC0 FADC GPTA0 STM FPU Flash Ext. Int
2 4 3 3 4 4 6 4 2 38 2 1 1 2
2 2 SRNs 4 SRNs 3 SRNs 3 SRNs 4 SRNs 4 SRNs 6 SRNs 4 SRNs 2 SRNs 38 SRNs 2 SRNs 1 SRN 1 SRN 2 SRNs 2 4 4 3 3 3 3 4 4 4 4 6 6 4 4 2 2 38 38 2 2 1 1 1 1 2 2 1 1 1 1 4 4 1 1 1 1 5 5 5 5 2 5
PIPN
Service Req. Nodes 5 SRNs 5 SRNs 2 SRNs 5 SRNs 5 5 2 5
PCP2
CPU Interrupt Control Unit ICU Int. Req. PIPN
Software and Breakpoint Interrupts CPU
Int. Ack. CCPN
Service Req. Nodes 1 SRN 1 SRN 4 SRNs 1 SRN 1 SRN 1 1 4 1 1
Service Requestors LBCU SBCU DMA Cerberus DMA Bus
1) MultiCAN module and the 6 SRNs are not applicable to TC1163.
TC1163/TC1164 Interrupt System
Figure 3-3
Block Diagram of the TC1163/TC1164 Interrupt System
Data Sheet
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Preliminary Functional Description
3.8
Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1)
Figure 3-4 shows a global view of the functional blocks and interfaces of the two Asynchronous/Synchronous Serial Interfaces, ASC0 and ASC1.
Clock Control
fASC
A2 RXD_I0 RXD_I1 RXD_O TXD_O A2 A2 P3.12 / RXD0B P3.13 / TXD0B A2 P3.0 / RXD0A P3.1 / TXD0A
Address Decoder EIR TBIR TIR RIR
ASC0 Module (Kernel)
Interrupt Control
ASC0_RDR To DMA ASC0_TDR
Port 3 Control
RXD_I0 ASC1 Module (Kernel) EIR TBIR TIR RIR RXD_I1 RXD_O TXD_O Interrupt Control
P3.9 / A2 RXD1A A2 P3.8 / TXD1A
P3.14 / A2 RXD1B A2 P3.15 / TXD1B
To DMA
ASC1_RDR ASC1_TDR
MCB06211c
Figure 3-4
Block Diagram of the ASC Interfaces
The ASC provides serial communication between the TC1163/TC1164 and other microcontrollers, microprocessors, or external peripherals. The ASC supports full-duplex asynchronous communication and half-duplex synchronous communication. In Synchronous Mode, data is transmitted or received synchronous to a shift clock that is generated by the ASC internally. In Asynchronous Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be
Data Sheet 53 V1.0, 2008-04
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Preliminary Functional Description
selected. Parity, framing, and overrun error detection are provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. For multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator provides the ASC with a separate serial clock signal, which can be accurately adjusted by a prescaler implemented as fractional divider. Features * Full-duplex asynchronous operating modes - 8-bit or 9-bit data frames, LSB first - Parity-bit generation/checking - One or two stop bits - Baud rate from 5.0 Mbit/s to 1.19 bit/s (@ 80 MHz module clock) - Multiprocessor mode for automatic address/data byte detection - Loop-back capability Half-duplex 8-bit synchronous operating mode - Baud rate from 10.0 Mbit/s to 813.8 bit/s (@ 80 MHz module clock) Double-buffered transmitter/receiver Interrupt generation - On a transmit buffer empty condition - On a transmit last bit of a frame condition - On a receive buffer full condition - On an error condition (frame, parity, overrun error)
* * *
Data Sheet
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Preliminary Functional Description
3.9
High-Speed Synchronous Serial Interfaces (SSC0 and SSC1)
Figure 3-5 shows a global view of the functional blocks and interfaces of the two highspeed Synchronous Serial Interfaces, SSC0 and SSC1.
MRSTA MRSTB MTSR MTSRA MTSRB MRST SCLKA SCLKB SCLK SLSI1 Slave SLSI[7:2] 1 ) SLSO[2:0] SSC0_RDR To DMA SSC0_TDR M/S Select 1 ) Enable
1)
fSSC 0
Clock Control
A2 P3.4 /MTSR0
Master
fC L C0
Slave
A2 P3.3 /MRST0
Address Decoder SSC0 Module (Kernel)
A2 P3.2 /SCLK0
Slave Master
Interrupt Control
EIR TIR RIR
Port 3 Control
A2 P3.7 /SLSI0 P3.5 /SLSO00 / A2 SLSO10 / SLSO00 AND SLSO10 A2 P3.6 /SLSO01 / SLSO11 / SLSO01 AND SLSO11 P3.7 /SLSO02 / A2 SLSO12 A2 P3.8 /SLSO06
Master
SLSO[5:3] SLSO6 SLSO7 1)
fSSC 1
Clock Control
SLSO[2:0] SLSO[5:3] Master SLSO6 1) SLSO7
A2 P2.1 /SLSO03 / SLSO13 P2.8 /SLSO04 / A2 SLSO14 A2 P2.9 /SLSO05 / SLSO15
fC L C1
Address Decoder
SLSI1 Slave EIR TIR RIR SSC1 Module (Kernel) SLSI[7:2] MRSTA MRSTB MTSR MTSRA MTSRB MRST
1)
Port 2 Control
A1 P2.13 /SLSI1
A2 P2.12 /MTSR1A
Interrupt Control
Master
A2 P2.10 /MRST1A A2 P2.11 /SCLK1A A2 P1.10 /SLSO17
To DMA
SSC1_RDR SSC1_TDR M/S Select
1)
Slave
Enable 1 ) Slave Master
1) These lines are not connected
SCLKA SCLKB SCLK
Port 1 Control
A2 P1.8 /MTSR1B A2 P1.9 /MRST1B A2 P1.11 /SCLK1B
MCB06225_c
Figure 3-5
Data Sheet
Block Diagram of the SSC Interfaces
55 V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
The SSC supports full-duplex and half-duplex serial synchronous communication up to 40.0 MBaud (@ 80 MHz module clock). The serial clock signal can be generated by the SSC itself (Master Mode) or can be received from an external master (Slave Mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A shift clock generator provides the SSC with a separate serial clock signal. Seven slave select inputs are available for Slave Mode operation. Eight programmable slave select outputs (chip selects) are supported in Master Mode. Features * Master and Slave Mode operation - Full-duplex or half-duplex operation - Automatic pad control possible Flexible data format - Programmable number of data bits: 2 to 16 bits - Programmable shift direction: LSB or MSB shift first - Programmable clock polarity: Idle low or idle high state for the shift clock - Programmable clock/data phase: Data shift with leading or trailing edge of the shift clock Baud rate generation from 40.0 Mbit/s to 610.36 bit/s (@ 80 MHz module clock) Interrupt generation - On a transmitter empty condition - On a receiver full condition - On an error condition (receive, phase, baud rate, transmit error) Flexible SSC pin configuration Seven slave select inputs SLSI[7:1] in Slave Mode Eight programmable slave select outputs SLSO[7:0] in Master Mode - Automatic SLSO generation with programmable timing - Programmable active level and enable control
*
* *
* * *
Data Sheet
56
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.10
Micro Second Bus Interface (MSC0)
The MSC interface provides a serial communication link typically used to connect power switches or other peripheral devices. The serial communication link includes a fast synchronous downstream channel and a slow asynchronous upstream channel. Figure 3-6 shows a global view of the MSC interface signals.
SR15 (from CAN)
fMSC0
Clock Control
FCLP FCLN Downstream Channel SOP SON
fCLC0
C FCLP0A C FCLN0 C SOP0A C SON0 A2 P2.11 / FCLP0B A2 P2.12 / SOP0B
Address Decoder
Interrupt Control To DMA
SR[1:0]
MSC0 Module (Kernel)
EN0 EN1 Port 2 Control
A2 P2.8 / EN00 A2 P2.9 / EN01
SR[3:2] 16 Upstream Channel 16
ALTINL[15:0] (from GPTA) ALTINH[15:0] EMGSTOPMSC (from SCU)
SDI[0]1)
A1 P2.13 / SDI0
1) SDI[7:1] are connected to high level
MCA06255
Figure 3-6
Block Diagram of the MSC Interface
The downstream and upstream channels of the MSC module communicate with the external world via nine I/O lines. Eight output lines are required for the serial communication of the downstream channel (clock, data, and enable signals). One out of eight input lines SDI[7:0] is used as serial data input signal for the upstream channel. The source of the serial data to be transmitted by the downstream channel can be MSC register contents or data that is provided at the ALTINL/ALTINH input lines. These input lines are typically connected to other on-chip peripheral units (for example with a timer unit like the GPTA). An emergency stop input signal makes it possible to set bits of the serial data stream to dedicated values in emergency cases.
Data Sheet 57 V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
Clock control, address decoding, and interrupt service request control are managed outside the MSC module kernel. Service request outputs are able to trigger an interrupt or a DMA request. Features * * Fast synchronous serial interface to connect power switches in particular, or other peripheral devices via serial buses High-speed synchronous serial transmission on downstream channel - Serial output clock frequency: fFCL = fMSC/2 - Fractional clock divider for precise frequency control of serial clock fMSC - Command, data, and passive frame types - Start of serial frame: Software-controlled, timer-controlled, or free-running - Programmable upstream data frame length (16 or 12 bits) - Transmission with or without SEL bit - Flexible chip select generation indicates status during serial frame transmission - Emergency stop without CPU intervention Low-speed asynchronous serial reception on upstream channel - Baud rate: fMSC divided by 4, 8, 16, 32, 64, 128, or 256 - Standard asynchronous serial frames - Parity error checker - 8-to-1 input multiplexer for SDI lines - Built-in spike filter on SDI lines
*
Data Sheet
58
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.11
MultiCAN Controller (CAN)
Note: Section 3.11 is not applicable to TC1163. Figure 3-7 shows a global view of the MultiCAN module with its functional blocks and interfaces.
fCAN
Clock Control
MultiCAN Module Kernel
fCLC
Address Decoder
Message Object Buffer 64 Objects
DMA INT_O [1:0] INT_O [5:2] INT_O15
Linked List Control
CAN Node 1 CAN Node 0
TXDC1 RXDC1 TXDC0 RXDC0 Port 3 Control
P3.15 / TXDCAN1 P3.14 / A2 RXDCAN1 A2 P3.13 / TXDCAN0 P3.12 / A2 RXDCAN0 A2
Interrupt Control
CAN Control
MCA06281
Figure 3-7
Block Diagram of MultiCAN Module
The MultiCAN module contains two independently-operating CAN nodes with Full-CAN functionality that are able to exchange Data and Remote Frames via a gateway function. Transmission and reception of CAN frames is handled in accordance with CAN specification V2.0 B (active). Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Both CAN nodes share a common set of message objects. Each message object can be individually allocated to one of the CAN nodes. Besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build gateways between the CAN nodes or to setup a FIFO buffer. The message objects are organized in double-chained linked lists, where each CAN node has its own list of message objects. A CAN node stores frames only into message objects that are allocated to the message object list of the CAN node, and it transmits only messages belonging to this message object list. A powerful, command-driven list controller performs all message object list operations.
Data Sheet
59
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
The bit timings for the CAN nodes are derived from the module timer clock (fCAN), and are programmable up to a data rate of 1 Mbit/s. External bus transceivers are connected to a CAN node via a pair of receive and transmit pins. MultiCAN Features * * * * * * * CAN functionality conforms to CAN specification V2.0 B active for each CAN node (compliant to ISO 11898) Two independent CAN nodes 64 independent message objects (shared by the CAN nodes) Dedicated control registers for each CAN node Data transfer rate up to 1Mbit/s, individually programmable for each node Flexible and powerful message transfer control and error handling capabilities Full-CAN functionality: message objects can be individually - assigned to one of the two CAN nodes - configured as transmit or receive object - configured as message buffer with FIFO algorithm - configured to handle frames with 11-bit or 29-bit identifiers - provided with programmable acceptance mask register for filtering - monitored via a frame counter - configured for Remote Monitoring Mode Automatic Gateway Mode support 6 individually programmable interrupt nodes CAN analyzer mode for bus monitoring
* * *
Data Sheet
60
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.12
Micro Link Serial Bus Interface (MLI0)
The Micro Link Interface is a fast synchronous serial interface that allows data exchange between microcontrollers of the 32-bit AUDO microcontroller family without intervention of a CPU or other bus masters. Figure 3-8 shows how two microcontrollers are typically connected together via their MLI interfaces. The MLI operates in both microcontrollers as a bus master on the system bus.
Controller 1 CPU
Controller 2 CPU
Peripheral A
Peripheral B
Peripheral C
Peripheral D
Memory System Bus
MLI
MLI System Bus
Memory
MCA06061
Figure 3-8 Features * * * * * * * *
Typical Micro Link Interface Connection
*
Synchronous serial communication between MLI transmitters and MLI receivers located on the same or on different microcontroller devices Automatic data transfer/request transactions between local/remote controller Fully transparent read/write access supported (= remote programming) Complete address range of remote controller available Specific frame protocol to transfer commands, addresses and data Error control by parity bit 32-bit, 16-bit, and 8-bit data transfers Programmable baud rates - MLI transmitter baud rate: max. fMLI/2 (= 40 Mbit/s @ 80 MHz module clock) - MLI receiver baud rate: max. fMLI Multiple remote (slave) controllers are supported
MLI transmitter and MLI receiver communicate with other off-chip MLI receivers and MLI transmitters via a 4-line serial I/O bus each. Several I/O lines of these I/O buses are available outside the MLI module kernel as four-line output or input buses.
Data Sheet 61 V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
Figure 3-9 shows a global view of the functional blocks of the MLI module with its interfaces.
A2 P2.0 / TCLK0 TCLK TREADYA TREADYB TREADYD TVALIDA TVALIDB TVALIDD TDATA Port 2 Control A2 P2.1 / TREADY0A A2 P2.2 / TVALID0A A2 P2.3 / TDATA0 A1 P2.4 / RCLK0A A2 P2.5 / RREADY0A A1 P2.6 / RVALID0A RCLKA RCLKB RCLKD SR[4:7] Receiver RREADYA RREADYB RREADYD RVALIDA RVALIDB RVALIDD RDATAA RDATAB RDATAD Port 5 Control A2 P5.15 / TCLK0 A2 P5.14 / TREADY0B A2 P5.13 / TVALID0B A2 P5.12 / TDATA0 A2 P5.11 / RCLK0B A2 P5.10 / RREADY0B A2 P5.9 / RVALID0B A2 P5.8 / RDATA0B
TC 1163/TC1164 MLI Block Diagram
Clock Control
fML I0
Address Decoder MLI 0 Module (Kernel)
Transmitter
Interrupt Control
SR[3:0]
A1 P2.7 / RDATA0A
To DMA
Cerberus
BRKOUT
Figure 3-9
Block Diagram of the MLI Module
Data Sheet
62
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.13
General Purpose Timer Array
The GPTA provides a set of timer, compare, and capture functionalities that can be flexibly combined to form signal measurement and signal generation units. They are optimized for tasks typical of electrical motor control applications, but can also be used to generate simple and complex signal waveforms needed in other industrial applications. The TC1163/TC1164 contains one General Purpose Timer Array (GPTA0). Figure 3-10 shows a global view of the GPTA module.
GPTA Clock Generation Unit FPC0 FPC1 FPC2 FPC3 FPC4 FPC5 PDL1 DCM3 Clock Conn. PDL0 DCM1 DCM2 DIGITAL PLL DCM0
fGPTA Clock Distribution Unit
GT0 GT1 GTC00 GTC01 GTC02 GTC03 Global Timer Cell Array GTC30 GTC31
Clock Bus
Signal Generation Unit
LTC00 LTC01 LTC02 LTC03 Local Timer Cell Array LTC62 LTC63
I/O Line Sharing Unit Interrupt Sharing Unit
MCB06063
Figure 3-10 Block Diagram of the GPTA Module
Data Sheet 63 V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.13.1
Functionality of GPTA0
The General Purpose Timer Array GPTA0 provides a set of hardware modules required for high-speed digital signal processing: * * * * * * Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation. Phase Discrimination Logic units (PDL) decode the direction information output by a rotation tracking system. Duty Cycle Measurement Cells (DCM) provide pulse-width measurement capabilities. A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA module clock ticks during an input signal's period. Global Timer units (GT) driven by various clock sources are implemented to operate as a time base for the associated Global Timer Cells. Global Timer Cells (GTC) can be programmed to capture the contents of a Global Timer on an external or internal event. A GTC may also be used to control an external port pin depending on the result of an internal compare operation. GTCs can be logically concatenated to provide a common external port pin with a complex signal waveform. Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may also be logically tied together to drive a common external port pin with a complex signal waveform. LTCs -- enabled in Timer Mode or Capture Mode -- can be clocked or triggered by various external or internal events.
*
Input lines can be shared by an LTC and a GTC to trigger their programmed operation simultaneously. The following list summarizes the specific features of the GPTA unit. Clock Generation Unit * Filter and Prescaler Cell (FPC) - Six independent units - Three basic operating modes: Prescaler, Delayed Debounce Filter, Immediate Debounce Filter - Selectable input sources: Port lines, GPTA module clock, FPC output of preceding FPC cell - Selectable input clocks: GPTA module clock, prescaled GPTA module clock, DCM clock, compensated or uncompensated PLL clock - fGPTA/2 maximum input signal frequency in Filter Modes Phase Discriminator Logic (PDL) - Two independent units - Two operating modes (2- and 3-sensor signals) - fGPTA/4 maximum input signal frequency in 2-sensor Mode, fGPTA/6 maximum input signal frequency in 3-sensor Mode
64 V1.0, 2008-04
*
Data Sheet
TC1163/TC1164
Preliminary * Functional Description
*
*
Duty Cycle Measurement (DCM) - Four independent units - 0 - 100% margin and time-out handling - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Digital Phase Locked Loop (PLL) - One unit - Arbitrary multiplication factor between 1 and 65535 - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Clock Distribution Unit (CDU) - One unit - Provides nine clock output signals: fGPTA, divided fGPTA clocks, FPC1/FPC4 outputs, DCM clock, LTC prescaler clock
Signal Generation Unit * Global Timers (GT) - Two independent units - Two operating modes (Free-Running Timer and Reload Timer) - 24-bit data width - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Global Timer Cell (GTC) - 32 units related to the Global Timers - Two operating modes (Capture, Compare and Capture after Compare) - 24-bit data width - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency Local Timer Cell (LTC) - 64 independent units - Three basic operating modes (Timer, Capture and Compare) for 63 units - Special compare modes for one unit - 16-bit data width - fGPTA maximum resolution - fGPTA/2 maximum input signal frequency
*
*
Interrupt Control Unit * 111 interrupt sources, generating up to 38 service requests
Data Sheet
65
V1.0, 2008-04
TC1163/TC1164
Preliminary I/O Sharing Unit * Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and MSC interface Functional Description
Data Sheet
66
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.14
Analog-to-Digital Converter (ADC0)
Section 3.14 shows the global view of the ADC module with its functional blocks and interfaces and the features which are provided by the module.
VDDM VDD VAGND0 VSS VSSM VAREF0 fADC
Clock Control GPRS EMUX0 EMUX1 ASGT SW0TR, SW0GT External ETR, EGT Request Unit QTR, QGT (SCU) TTR, TGT ADC0 Module Kernel AIN0 Group 0 AIN15 AIN16 Group 1 AIN30 AIN31 Die Temperature Measurement SCU_CON.DTSON
MCA06427
A1 Port 1 Control
fCLC
P1.14 / AD0EMUX2 (GRPS)
A1 P1.13 /AD0EMUX1 A1 P1.12 /AD0EMUX0 8 2 6 D D D D D From Ports From MSC0 From GPTA AN0 AN15 AN16 AN30 AN31
Address Decoder
To DMA
SR[7:4]
Analog Multiplexer
Interrupt Control
SR[3:0]
0
1
Figure 3-11 Block Diagram of the ADC Module The ADC module has 16 analog input channels. An analog multiplexer selects the input line for the analog input channels from among 32 analog inputs. Additionally, an external analog multiplexer can be used for analog input extension. External Clock control, address decoding, and service request (interrupt) control are managed outside the ADC module kernel. External trigger conditions are controlled by an External Request Unit. This unit generates the control signals for auto-scan control (ASGT), software trigger control (SW0TR, SW0GT), the event trigger control (ETR, EGT), queue control (QTR, QGT), and timer trigger control (TTR, TGT). An automatic self-calibration adjusts the ADC module to changing temperatures or process variations. Figure 3-11 shows the global view of the ADC module with its functional blocks and interfaces.
Data Sheet
67
V1.0, 2008-04
TC1163/TC1164
Preliminary Features * * * * * * * * * * * * * * * * * * 8-bit, 10-bit, 12-bit A/D conversion Conversion time below 2.5s @ 10-bit resolution Extended channel status information on request source Successive approximation conversion method Total Unadjusted Error (TUE) of 2 LSB @ 10-bit resolution Integrated sample & hold functionality Direct control of up to 16 analog input channels Dedicated control and status registers for each analog channel Powerful conversion request sources Selectable reference voltages for each channel Programmable sample and conversion timing schemes Limit checking Flexible ADC module service request control unit Automatic control of external analog multiplexers Equidistant samples initiated by timer External trigger and gating inputs for conversion requests Power reduction and clock control feature On-chip die temperature sensor output voltage measurement Functional Description
Data Sheet
68
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.15
Fast Analog-to-Digital Converter Unit (FADC)
The on-chip FADC module of the TC1163/TC1164 basically is a 2-channel A/D converter with 10-bit resolution that operates by the method of the successive approximation. As shown in Figure 3-12, the main FADC functional blocks are: * * * * * * * * * The Input Stage -- contains the differential inputs and the programmable amplifier The A/D Converter -- is responsible for the analog-to-digital conversion The Data Reduction Unit -- contains programmable antialiasing and data reduction filters The Channel Trigger Control block -- determines the trigger and gating conditions for the two FADC channels The Channel Timers -- can independently trigger the conversion of each FADC channel The A/D Control block is responsible for the overall FADC functionality
The FADC module is supplied by the following power supply and reference voltage lines:
VDDMF/VDDMF:FADC Analog Part Power Supply (3.3 V) VDDAF/VDDAF:FADC Analog Part Logic Power Supply (1.5 V) VFAREF/VFAGND:FADC Reference Voltage (3.3 V)/FADC Reference Ground
Data Sheet
69
V1.0, 2008-04
TC1163/TC1164
Preliminary
VFAREF VDDAF VDDMF VFAGND VSSAF VSSMF fFADC
Clock Control Address Decoder Interrupt Control SR[1:0] FADC Module Kernel
Functional Description
fCLC
FAIN0P FAIN0N FAIN1P FAIN1N D AN32 D AN33 D AN34 D AN35
SR[3:2] DMA
GPTA0
OUT1 OUT9 OUT18 OUT26 OUT2 OUT10 OUT19 OUT27 PDOUT2
A1 P3.10 / REQ0 A1 P3.11 / REQ1 GS[7:0] TS[7:0] A1 P0.14 / REQ4 A1 P0.15 / REQ5
External Request Unit (SCU)
PDOUT3
MCA06445
Figure 3-12 Block Diagram of the FADC Module Features * * * * * * * * * * * Extreme fast conversion, 21 cycles of fFADC clock (262.5 ns @ fFADC = 80 MHz) 10-bit A/D conversion - Higher resolution by averaging of consecutive conversions is supported Successive approximation conversion method Two differential input channels Offset and gain calibration support for each channel Differential input amplifier with programmable gain of 1, 2, 4 and 8 for each channel Free-running (Channel Timers) or triggered conversion modes Trigger and gating control for external signals Built-in Channel Timers for internal triggering Channel timer request periods independently selectable for each channel Selectable, programmable anti-aliasing and data reduction filter block
70 V1.0, 2008-04
Data Sheet
TC1163/TC1164
Preliminary Functional Description
3.16
System Timer
The TC1163/TC1164's STM is designed for global system timing applications requiring both high precision and long period. Features * * * * * * * Free-running 56-bit counter All 56 bits can be read synchronously Different 32-bit portions of the 56-bit counter can be read synchronously Flexible interrupt generation based on compare match with partial STM content Driven by maximum 80 MHz (= fSYS, default after reset = fSYS/2) Counting starts automatically after a reset operation STM is reset by: - Watchdog reset - Software reset (RST_REQ.RRSTM must be set) - Power-on reset STM (and clock divider STM_CLC.RMC) is not reset at a hardware reset (HDRST = 0) STM can be halted in debug/suspend mode (via STM_CLC register)
* *
The STM is an upward counter, running either at the system clock frequency fSYS or at a fraction of it. The STM clock frequency is fSTM = fSYS/RMC with RMC = 0-7 (default after reset is fSTM = fSYS/2, selected by RMC = 010B). RMC is a bit field in register STM_CLC. In case of a power-on reset, a watchdog reset, or a software reset, the STM is reset. After one of these reset conditions, the STM is enabled and immediately starts counting up. It is not possible to affect the content of the timer during normal operation of the TC1163/TC1164. The timer registers can only be read but not written to. The STM can be optionally disabled for power-saving purposes, or suspended for debugging purposes via its clock control register. In suspend mode of the TC1163/TC1164 (initiated by writing an appropriate value to STM_CLC register), the STM clock is stopped but all registers are still readable. Due to the 56-bit width of the STM, it is not possible to read its entire content with one instruction. It needs to be read with two load instructions. Since the timer would continue to count between the two load operations, there is a chance that the two values read are not consistent (due to possible overflow from the low part of the timer to the high part between the two read operations). To enable a synchronous and consistent reading operation of the STM content, a capture register (STM_CAP) is implemented. It latches the content of the high part of the STM each time when one of the registers STM_TIM0 to STM_TIM5 is read. Thus, STM_CAP holds the upper value of the timer at exactly the same time when the lower part is read. The second read operation would then read the content of the STM_CAP to get the complete timer value.
Data Sheet
71
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
The STM can also be read in sections from seven registers, STM_TIM0 through STM_TIM6, that select increasingly higher-order 32-bit ranges of the STM. These can be viewed as individual 32-bit timers, each with a different resolution and timing range. The content of the 56-bit System Timer can be compared with the content of two compare values stored in the STM_CMP0 and STM_CMP1 registers. Interrupts can be generated on a compare match of the STM with the STM_CMP0 or STM_CMP1 registers. The maximum clock period is 256 x fSTM. At fSTM = 80 MHz, for example, the STM counts 28.56 years before overflowing. Thus, it is capable of timing the entire expected product life-time of a system without overflowing continuously. Figure 3-13 shows an overview on the System Timer with the options for reading parts of the STM contents.
Data Sheet
72
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
STM Module
31 23 15 7 0
STM_CMP0
Compare Register 0
31 23 15 7 0
STM_CMP1 STMIR1 Interrupt Control
55 47 39 31
Compare Register1
23 15 7 0
STMIR0
56-Bit System Timer
Enable / Disable Clock Control
00H 00H STM_TIM5
STM_CAP STM_TIM6
fSTM
Address Decoder
STM_TIM4 STM_TIM3
PORST STM_TIM2 STM_TIM1 STM_TIM0
MCB06185
Figure 3-13 General Block Diagram of the STM Module Registers
Data Sheet
73
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.17
Watchdog Timer
The WDT provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC1163/TC1164 in a user-specified time period. When enabled, the WDT will cause the TC1163/TC1164 system to be reset if the WDT is not serviced within a userprogrammable time period. The CPU must service the WDT within this time interval to prevent the WDT from causing a TC1163/TC1164 system reset. Hence, routine service of the WDT confirms that the system is functioning as expected. In addition to this standard "Watchdog" function, the WDT incorporates the End-ofInitialization (Endinit) feature and monitors its modifications. A system-wide line is connected to the WDT_CON0.ENDINIT bit, serving as an additional write-protection for critical registers (besides Supervisor Mode protection). Registers protected via this line can only be modified when Supervisor Mode is active and bit ENDINIT = 0. A further enhancement in the TC1163/TC1164's WDT is its reset prewarning operation. Instead of resetting the device upon the detection of an error immediately (the way that standard Watchdogs do), the WDT first issues a Non-Maskable Interrupt (NMI) to the CPU before resetting the device at a specified time period later. This step gives the CPU a chance to save the system state to the memory for later investigation of the cause of the malfunction; an important aid in debugging. Features * * * * * * * * * * 16-bit Watchdog counter Selectable input frequency: fSYS/256 or fSYS/16384 16-bit user-definable reload value for normal Watchdog operation, fixed reload value for Time-Out and Prewarning Modes Incorporation of the ENDINIT bit and monitoring of its modifications Sophisticated Password Access mechanism with fixed and user-definable password fields Proper access always requires two write accesses. The time between the two accesses is monitored by the WDT and is limited. Access Error Detection: Invalid password (during first access) or invalid guard bits (during second access) trigger the Watchdog reset generation Overflow Error Detection: An overflow of the counter triggers the Watchdog reset generation. Watchdog function can be disabled; access protection and ENDINIT monitor function remain enabled. Double Reset Detection: If a Watchdog induced reset occurs twice, a severe system malfunction is assumed and the TC1163/TC1164 is held in reset until a power-on or hardware reset occurs. This prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that system initialization could not even be performed.
74 V1.0, 2008-04
Data Sheet
TC1163/TC1164
Preliminary * Functional Description
Important debugging support is provided through the reset prewarning operation by first issuing an NMI to the CPU before finally resetting the device after a certain period of time.
3.18
System Control Unit
The System Control Unit (SCU) of the TC1163/TC1164 handles several system control tasks. The system control tasks of the SCU are: * * * * * * * * * * * * * * Clock system selection and control Reset and boot operation control Power management control Configuration input sampling External Request Unit System clock output control On-chip SRAM parity control Pad driver temperature compensation control Emergency stop input control for GPTA outputs GPTA input IN1 control Pad test mode control for dedicated pins ODCS level 2 trace control NMI control Miscellaneous SCU control
Data Sheet
75
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.19
Boot Options
The TC1163/TC1164 booting schemes provide a number of different boot options for the start of code execution. Table 3-7 shows the boot options available in the TC1163/TC1164. Table 3-7 BRKIN TC1163/TC1164 Boot Selections HWCFG [3:0] TESTMODE Type of Boot BootROM Exit Jump Address D400 0000H
Normal Boot Options 1 0000B 0001B1) 1 Enter bootstrap loader mode 1: Serial ASC0 boot via ASC0 pins Enter bootstrap loader mode 2: Serial CAN boot via P3.12 and P3.13 pins Start from internal PFLASH A000 0000H Alternate boot mode (ABM): Start Defined in from internal PFLASH after CRC ABM header check is correctly executed; enter or D400 0000H a serial bootstrap loader mode2) if CRC check fails Enter bootstrap loader mode 3: Serial ASC0 boot via P3.12 and P3.13 pins Reserved; execute stop loop 1 irrel. Tri-state chip Reserved; execute stop loop D400 0000H
0010B 0011B
1111B
others Debug Boot Options 0 0000B others
- - -
1) This option is not applicable to TC1163. 2) The type of the alternate bootstrap loader mode is selected by the value of the SCU_SCLIR.SWOPT[2:0] bit field, which contains the levels of the P0.[2:0] latched in with the rising edge of the HDRST.
Data Sheet
76
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.20
Power Management System
The TC1163/TC1164 power management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. There are three power management modes: * * * Run Mode Idle Mode Sleep Mode
The operation of each system component in each of these states can be configured by software. The power-management modes provide flexible reduction of power consumption through a combination of techniques, including stopping the CPU clock, stopping the clocks of other system components individually, and individually clockspeed reduction of some peripheral components. Besides these explicit software-controlled power-saving modes, special attention has been paid to automatic power-saving in those operating units which are not required at a certain point of time, or idle in the TC1163/TC1164. In that case, they are shut off automatically until their operation is required again. Table 3-8 describes the features of the power management modes. Table 3-8 Mode Run Idle Power Management Mode Summary Description The system is fully operational. All clocks and peripherals are enabled, as determined by software. The CPU clock is disabled, waiting for a condition to return it to Run Mode. Idle Mode can be entered by software when the processor has no active tasks to perform. All peripherals remain powered and clocked. Processor memory is accessible to peripherals. A reset, Watchdog Timer event, a falling edge on the NMI pin, or any enabled interrupt event will return the system to Run Mode. The system clock signal is distributed only to those peripherals programmed to operate in Sleep Mode. The other peripheral module will be shut down by the suspend signal. Interrupts from operating peripherals, the Watchdog Timer, a falling edge on the NMI pin, or a reset event will return the system to Run Mode. Entering this state requires an orderly shut-down controlled by the Power Management State Machine.
Sleep
In typical operation, Idle Mode and Sleep Mode may be entered and exited frequently during the run time of an application. For example, system software will typically cause the CPU to enter Idle Mode each time it has to wait for an interrupt before continuing its tasks. In Sleep Mode and Idle Mode, wake-up is performed automatically when any
Data Sheet 77 V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
enabled interrupt signal is detected, or when the count value (WDT_SR.WDTTIM) changes from 7FFFH to 8000H.
3.21
On-Chip Debug Support
Figure 3-14 shows a block diagram of the TC1163/TC1164 OCDS system.
OCDS L1
BCU
OCDS L2
PCP
OCDS L1
SPB Peripheral Unit 1
Multiplexer
DMA L2
OCDS2[15:0]
16
OCDS OCDS TriCore L2 L1 Watchdog Timer
Enable, Control and Reset
SPB Peripheral Unit n
Break and Suspend Signals
TDI TMS TCK TRST BRKIN BRKOUT JTAG Controller
Cerberus
TDO
DMA
OSCU
JDI Debug I/F MCBS Break Switch
System Peripheral Bus
MCB06195
Figure 3-14 OCDS System Block Diagram The TC1163/TC1164 basically supports two levels of debug operation: * * OCDS Level 1 debug support OCDS Level 2 debug support
Data Sheet
78
V1.0, 2008-04
TC1163/TC1164
Preliminary OCDS Level 1 Debug Support The OCDS Level 1 debug support is mainly assigned for real-time software debugging purposes which have a demand for low-cost standard debugger hardware. The OCDS Level 1 is based on a JTAG interface that is used by the external debug hardware to communicate with the system. The on-chip Cerberus module controls the interactions between the JTAG interface and the on-chip modules. The external debug hardware may become master of the internal buses, and read or write the on-chip register/memory resources. The Cerberus also makes it possible to define breakpoint and trigger conditions as well as to control user program execution (run/stop, break, single-step). OCDS Level 2 Debug Support The OCDS Level 2 debug support makes it possible to implement program tracing capabilities for enhanced debuggers by extending the OCDS Level 1 debug functionality with an additional 16-bit wide trace output port with trace clock. With the trace extension, the following four trace capabilities are provided (only one of the four trace capabilities can be selected at a time): * * * * Trace of the CPU program flow Trace of the PCP2 program flow Trace of the DMA Controller transaction requests Trace of the DMA Controller Move Engine status information Functional Description
Data Sheet
79
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.22
* * * * * *
Clock Generation and PLL
The TC1163/TC1164 clock system performs the following functions: Acquires and buffers incoming clock signals to create a master clock frequency Distributes in-phase synchronized clock signals throughout the TC1163/TC1164's entire clock tree Divides a system master clock frequency into lower frequencies required by the different modules for operation. Dynamically reduces power consumption during operation of functional units Statically reduces power consumption through programmable power-saving modes Reduces electromagnetic interference (EMI) by switching off unused modules
The clock system must be operational before the TC1163/TC1164 can function, so it contains special logic to handle power-up and reset operations. Its services are fundamental to the operation of the entire system, so it contains special fail-safe logic. Features * * * * PLL operation for multiplying clock source by different factors Direct drive capability for direct clocking Comfortable state machine for secure switching between basic PLL, direct or prescaler operation Sleep and Power-Down Mode support
The TC1163/TC1164 Clock Generation Unit (CGU) as shown in Figure 3-15 allows a very flexible clock generation. It basically consists of an main oscillator circuit and a Phase- Locked Loop (PLL). The PLL can converts a low-frequency external clock signal from the oscillator circuit to a high-speed internal clock for maximum performance. The system clock fSYS is generated from an oscillator clock fOSC in either one of the four hardware/software selectable ways: * Direct Drive Mode (PLL Bypass): In Direct Drive Mode, the TC1163/TC1164 clock system is directly driven by an external clock signal. input, i.e. fCPU = fOSC and fSYS = fOSC. This allows operation of the TC1163/TC1164 with a reasonably small fundamental mode crystal. VCO Bypass Mode (Prescaler Mode): In VCO Bypass Mode, fCPU and fSYS are derived from fOSC by the two divider stages, P-Divider and K-Divider. The system clock fSYS is equal to fCPU. PLL Mode: In PLL Mode, the PLL is running. The VCO clock fVCO is derived from fOSC, divided by the P factor, multiplied by the PLL (N-Divider). The clock signals fCPU and fSYS are derived from fVCO by the K-Divider. The system clock fSYS is equal to fCPU. PLL Base Mode: In PLL Base Mode, the PLL is running at its VCO base frequency and fCPU and fSYS
*
*
*
Data Sheet
80
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
are derived from fVCO only by the K-Divider. In this mode, the system clock fSYS is equal to fCPU.
XTAL1 Oscillator Circuit XTAL2 Osc. Run Detect. fOSC
Clock Generation Unit (CGU) 1:1 Divider
1
P Divider
1
Phase Detect.
fVCO VCO
0
M U X
K:1 Divider
M U X
fSYS fCPU
N Divider PLL
Lock Detector
BYPASS
OGC MOSC OSCR
PDIV OSC [2:0] DISC
PLL_ LOCK
NDIV VCO_ VCO_ KDIV SYS PLL_ [6:0] SEL[1:0] BYPASS [3:0] FSL BYPASS
Register OSC_CON OSC_ BYPASS
Register PLL_CLC System Control Unit (SCU)
MCA06083
Figure 3-15 Clock Generation Unit Recommended Oscillator Circuits The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal oscillator or an external stable clock source. It basically consists of an inverting amplifier and a feedback element with XTAL1 as input, and XTAL2 as output. When using a crystal, a proper external oscillator circuitry must be connected to both pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 4 MHz to 25 MHz. Additionally, it is necessary to have two load capacitances CX1 and CX2, and depending on the crystal type, a series resistor RX2, to limit the current. A test resistor RQ may be temporarily inserted to measure the oscillation allowance (negative resistance) of the oscillator circuitry. RQ values are typically specified by the crystal vendor. The CX1 and CX2 values shown in Figure 3-16 can be used as starting points for the negative resistance evaluation and for non-productive systems. The exact values and related operating range are dependent on the crystal frequency and have to be determined and optimized together with the crystal vendor using the negative resistance method.
Data Sheet 81 V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
Oscillation measurement with the final target system is strongly recommended to verify the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin negative resistance) for the oscillator-crystal system. When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is left open (unconnected). The external clock frequency can be in the range of 0 - 40 MHz if the PLL is bypassed, and 4 - 40 MHz if the PLL is used. The oscillator can also be used in combination with a ceramic resonator. The final circuitry must also be verified by the resonator vendor. Figure 3-16 shows the recommended external oscillator circuitries for both operating modes, external crystal mode and external input clock mode. A block capacitor is recommended to be placed between VDDOSC/VDDOSC3 and VSSOSC.
V DDOSC
VDDOSC3
VDDOSC
V DDOSC3
XTAL1 4 - 25 MHz TC1163/TC1164 Oscillator
f OSC
External Clock Signal 4 - 40 MHz
XTAL1 TC1163/TC1164 Oscillator XTAL2
fOSC
RQ
R X2
XTAL2
CX1
CX2
Fundamental Mode Crystal
VSSOSC R X2 1)
0 0 0 0
V SSOSC
Crystal Frequency CX1, CX2 1) 4 MHz 8 MHz 12 MHz 16 - 25 MHz 33 18 12 10 pF pF pF pF
1) Note that these are evaluation start values!
TC1163/TC1164 Oscillator Circuitry
Figure 3-16 Oscillator Circuitries Note: For crystal operation, it is strongly recommended to measure the negative resistance in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier.
Data Sheet
82
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.23
* *
Power Supply
The TC1163/TC1164 has several power supply lines for different voltage classes: 1.5 V: Core logic, oscillator and A/D converter supply 3.3 V: I/O ports, Flash memories, oscillator, and A/D converter supply with reference voltages
Figure 3-17 shows the power supply concept of the TC1163/TC1164 with the power supply pins and its connections to the functional units.
VDDM
(3.3V)
VAREF
(3.3V)
VDDAF
(1.5V)
V DDMF
(3.3V)
VFAREF
(3.3V)
V SSM
2
V AGND
2
VSSAF
2
VSSMF
2
V FAGND
2 TC1163/TC1164
ADC
FADC
V SSA
1
(1.5 V) 1
V DDA
PLL Core
Ports
Flash Memories
OSC
9
7
8
1
3
V SS
V DD
(1.5 V)
V DDP
(3.3 V)
V DDFL3
3.3 V
V DDOSC3 (3.3 V) V DDOSC (1.5 V) V SSOSC
TC1163/TC1164 PwrSupply
Figure 3-17 Power Supply Concept of TC1163/TC1164
Data Sheet
83
V1.0, 2008-04
TC1163/TC1164
Preliminary Functional Description
3.24
Identification Register Values
Table 3-9 shows the address map and reset values of the TC1163/TC1164 Identification Registers. Table 3-9 Short Name SCU_ ID MANID CHIPID RTID SBCU_ID STM_ID CBS_ JDPID MSC0_ ID ASC0_ ID ASC1_ ID GPTA0_ ID DMA_ID CAN_ID
1)
TC1163/TC1164 Identification Registers Address F000 0008H F000 0070H F000 0074H F000 0078H F000 0108H F000 0208H F000 0408H F000 0808H F000 0A08H F000 0B08H F000 1808H F000 3C08H F000 4008H F010 0108H F010 0308H F010 0408H F010 C008H F010 C208H F7E0 FF08H F7E1 FE18H F800 0508H F800 2008H F87F FC08H F87F FD08H F87F FE08H F87F FF08H Reset Value 002C C002H 0000 1820H 0000 8B02H 0000 0001H 0000 0007H 0000 6A0AH 0000 C006H 0000 6307H 0028 C001H 0000 4402H 0000 4402H 0029 C004H 001A C012H 002B C012H 0000 4510H 0027 C012H 0030 C001H 0025 C006H 001B C001H 0015 C006H 000A C005H 002E C012H 0041 C002H 0008 C004H 000B C004H 000F C005H 000C C005H
84
Stepping - - - AA-Step AB-Step - - - - - - - - - - - - - - - - - - - - - -
V1.0, 2008-04
SSC0_ ID FADC_ ID ADC0_ID MLI0_ ID MCHK_ ID CPS_ID CPU_ID PMU_ID FLASH_ID DMI_ID PMI_ID LBCU_ID LFI_ID
Data Sheet
TC1163/TC1164
Preliminary
1) The address and reset value of CAN_ID is not applicable to TC1163.
Functional Description
Data Sheet
85
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4
Electrical Parameters
Chapter 4 provides the characteristics of the electrical parameters which are implementation-specific for the TC1163/TC1164.
4.1
General Parameters
The general parameters are described here to aid the users in interpreting the parameters mainly in Section 4.2 and Section 4.3. The absolute maximum ratings and its operating conditions are provided for the appropriate setting in the TC1163/TC1164.
4.1.1
Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the TC1163/TC1164 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column "Symbol": * CC Such parameters indicate Controller Characteristics which are a distinctive feature of the TC1163/TC1164 and must be regarded for a system design. SR Such parameters indicate System Requirements which must provided by the microcontroller system in which the TC1163/TC1164 designed in.
*
Data Sheet
86
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.1.2
Pad Driver and Pad Classes Summary
This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in Section 4.2.1. Table 4-1 Pad Driver and Pad Classes Overview Sub Class A1 (e.g. GPIO) A2 (e.g. serial I/Os) Speed Load Grade 6 MHz 40 MHz Leakage1) Termination No Series termination recommended Series termination recommended (for f > 25 MHz) Series termination recommended Parallel termination2), 100 10%
Class Power Type Supply A 3.3V LVTTL I/O, LVTTL outputs
100 pF 500 nA 50 pF 6 A
A3 80 (e.g. BRKIN, MHz/ BRKOUT) A4 (e.g. Trace Clock) C 3.3V LVDS - 80 MHz 50 MHz
50 pF
6 A
25 pF
6 A
-
D
-
Analog inputs, reference voltage inputs
1) Values are for TJmax = 125 C. 2) In applications where the LVDS pins are not used (disabled), these pins must be either left unconnected, or properly terminated with the differential parallel termination of 100 10%.
Data Sheet
87
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.1.3
Absolute Maximum Ratings
Table 4-2 shows the absolute maximum ratings of the TC1163/TC1164 parameters. Table 4-2 Parameter Ambient temperature Absolute Maximum Rating Parameters Symbol Limit Values Min. Max. 85 150 125 2.25 3.75 C C C V V V Under bias - Under bias - - Whatever is lower Whatever is lower Whatever is lower SR -40 SR -65 SR -40 SR - SR - SR -0.5 Unit Notes
TA Storage temperature TST Junction temperature TJ Voltage at 1.5 V power supply VDD pins with respect to VSS1) Voltage at 3.3 V power supply VDDP pins with respect to VSS2) Voltage on any Class A input VIN
pin and dedicated input pins with respect to VSS Voltage on any Class D analog input pin with respect to VAGND Voltage on any Class D analog input pin with respect to VSSAF CPU & LMB Bus Frequency FPI Bus Frequency
VDDP + 0.5
or max. 3.7
VAIN, VAREFx VAINF, VFAREF fCPU fSYS
SR -0.5
VDDM + 0.5
or max. 3.7
V
SR -0.5
VDDMF + 0.5 V or max. 3.7
803) 803)
SR - SR -
MHz - MHz
4)
1) Applicable for VDD, VDDOSC, VDDPLL, and VDDAF. 2) Applicable for VDDP, VDDFL3, VDDM, and VDDMF. 3) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter parameters. 4) The ratio between fCPU and fSYS is fixed at 1:1.
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > related VDD or VIN < VSS) the voltage on the related VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Data Sheet 88 V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.1.4
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct operation of the TC1163/TC1164. All parameters specified in the following table refer to these operating conditions, unless otherwise noted. Table 4-3 Parameter Operating Condition Parameters Symbol Limit Values Min. Digital supply voltage1) Max. 1.582) V 3.473) V - For Class A pins (3.3V 5%) - - - See separate specification Page 4-95, Page 4-102
6)
Unit Notes Conditions
VDD VDDOSC VDDP VDDOSC3 VDDFL3 VSS TA
-
SR SR
1.42 3.13
SR SR SR
3.13 0 -40 -
3.473) V V +85 - C -
Digital ground voltage Ambient temperature under bias Analog supply voltages
CPU clock Short circuit current Absolute sum of short circuit currents of a pin group (see Table 4-4) Absolute sum of short circuit currents of the device Inactive device pin current
fCPU ISC
|ISC|
SR SR SR
-4) -5 -
805) +5 20
MHz - mA mA See note7)
|ISC|
SR SR
- -1
100 1
mA mA
See note 7) Voltage on all power supply pins VDDx = 0 Depending on pin class
IID
External load capacitance
CL
SR
-
See pF DC chara cterist ics
Data Sheet
89
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
1) Digital supply voltages applied to the TC1163/TC1164 must be static regulated voltages which allow a typical voltage swing of 5%. 2) Voltage overshoot up to 1.7 V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 3) Voltage overshoot to 4 V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 4) The TC1163/TC1164 uses a static design, so the minimum operation frequency is 0 MHz. Due to test time restriction no lower frequency boundary is tested, however. 5) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter parameters. 6) Applicable for digital outputs. 7) See additional document "TC1796 Pin Reliability in Overload" for overload current definitions.
Data Sheet
90
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 4-4 Group 1 2 3 4 5 6 7 8 Electrical Parameters Pin Groups for Overload/Short-Circuit Current Sum Parameter Pins TRCLK, P5.[7:0], P0.[7:6], P0.[15:14] P0.[13:12], P0.[5:4], P2.[13:8], SOP0A, SON0, FCLP0A, FCLN0 P0.[11:8], P0.[3:0], P3.[13:11] P3[10:0], P3.[15:14] HDRST, PORST, NMI, TESTMODE, BRKIN, BRKOUT, BYPASS, TCK, TRST, TDO, TMS, TDI, P1.[7:4] P1.[3:0], P1.[11:8], P4.[3:0] P2.[7:0], P1.[14:12] P5.[15:8]
Data Sheet
91
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.2
DC Parameters
The electrical characteristics of the DC Parameters are detailed in this section.
4.2.1
Input/Output Pins
Table 4-5 provides the characteristics of the input/output pins of the TC1163/TC1164. Table 4-5 Parameter Input/Output DC-Characteristics (Operating Conditions apply) Symbol Limit Values Min. General Parameters Pull-up current1) |IPUH| CC 10 20 Pull-down current1) |IPDL| CC 10 20 Pin capacitance1) (Digital I/O) Input low voltage class A1/A2 pins 100 200 150 200 10 A A A A pF Max. Unit Test Conditions
VIN < VIHAmin;
class A1/A2/Input pads.
VIN < VIHAmin;
class A3/A4 pads.
VIN > VILAmax; class A1/A2/Input pads. VIN > VILAmax;
class A3/A4 pads.
CIO
CC -
f = 1 MHz TA = 25 C
- Whatever is lower
Input only Pads (VDDP = 3.13 to 3.47 V = 3.3V 5%)
VILA
SR SR
-0.3 0.64 x
0.34 x
V V
Input high voltage VIHA class A1/A2 pins Ratio VIL/VIH Input low voltage class A3 pins
VDDP VDDP+
0.3 or max. 3.6 - 0.8 - - 3000 6000
VDDP
CC 0.53
- V V V nA
- - -
2)5)
VILA3
SR SR
- 2.0
Input high voltage VIHA3 class A3 pins Input hysteresis Input leakage current
HYSA CC 0.1 x
VDDP IOZI
CC - ((VDDP/2)-1) < VIN < ((VDDP/2)+1) otherwise3)
Data Sheet
92
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 4-5 Parameter Electrical Parameters Input/Output DC-Characteristics (cont'd)(Operating Conditions apply) Symbol Limit Values Min. Output low voltage4) Max. 0.4 V Unit Test Conditions
Class A Pads (VDDP = 3.13 to 3.47 V = 3.3V 5%)
VOLA
CC -
IOL = 2 mA for strong driver
mode, (Not applicable to Class A1 pins) IOL = 1.8 mA for medium driver mode, A2 pads IOL = 1.4 mA for medium driver mode, A1 pads IOL = 370 A for weak driver mode
Output high voltage3)
VOHA
CC 2.4
-
V
IOH = -2 mA for strong
driver mode, (Not applicable to Class A1 pins) IOH = -1.8 mA for medium driver mode, A1/A2 pads IOH = -370 A for weak driver mode
VDDP 0.4
-
V
IOH = -1.4 mA for strong
driver mode, (Not applicable to Class A1 pins) IOH = -1 mA for medium driver mode, A1/A2 pads IOH = -280 A for weak driver mode
Input low voltage class A1/2 pins
VILA
SR SR
-0.3 0.64 x
0.34 x
V V
- Whatever is lower
Input high voltage VIHA class A1/2 pins Ratio VIL/VIH Input hysteresis
VDDP VDDP +
0.3 or 3.6 - -
VDDP
CC 0.53
- V
-
2)5)
HYSA CC 0.1 x
VDDP
Data Sheet
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TC1163/TC1164
Preliminary Table 4-5 Parameter Input leakage current Class A2/3/4 pins Input leakage current Class A1 pins Electrical Parameters Input/Output DC-Characteristics (cont'd)(Operating Conditions apply) Symbol Limit Values Min. Max. 3000 6000 nA ((VDDP/2)-1) < VIN <((VDDP/2)+1) otherwise3) 0 V IOZA24 CC -
IOZA1
CC -
500
nA
Class C Pads (VDDP = 3.13 to 3.47 V = 3.3V 5%) Output low voltage VOL Output high voltage CC 815 CC CC 150 CC 1075 CC 40 - 1545 600 1325 140 - - mV mV mV mV - -
VOH
Parallel termination 100 1%
Output differential VOD voltage Output offset voltage Class D Pads see ADC Characteristics
VOS
Output impedance R0
1) Not subject to production test, verified by design / characterization. 2) The pads that have spike filter function in the input path: PORST, HDRST, NMI do not have hysteresis. 3) Only one of these parameters is tested, the other is verified by design characterization 4) Max. resistance between pin and next power supply pin 25 for strong driver mode (verified by design characterization). 5) Function verified by design, value is not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise.
Data Sheet
94
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.2.2
Analog to Digital Converter (ADC0)
Table 4-6 provides the characteristics of the ADC module in the TC1163/TC1164. Table 4-6 Parameter Analog supply voltage ADC Characteristics (Operating Conditions apply) Symbol Min. Limit Values Typ. 3.3 1.5 Max. 3.471) V 1.58
2)
Unit
Test Conditions / Remarks - Power supply for ADC digital part, internal supply - -
VDDM VDD
SR 3.13 SR 1.42
V
Analog ground voltage
VSSM
SR -0.1
-
0.1
V
Analog reference VAREFx voltage 17) Analog reference VAGNDx ground 17) Analog reference VAREFxvoltage range5)17) VAGNDx Analog input voltage range VDDM supply current Power-up calibration time Internal ADC clocks Sample time
SR VAGNDx+ VDDM VDDM+ V 1V 0.05
1)3)4)
SR VSSMx 0.05V SR VDDM/2 SR VAGNDx SR CC -
0
VAREF V
-1V
-
VDDM
+ 0.05 - 2.5 - VAREFx V 4 3840 mA rms -
6)
VAIN IDDM tPUC
fADC
CLK
-
fBC fANA tS
CC 2 CC 0.5
- -
40 10
MHz fBC = fANA x 4 MHz fANA = fBC / 4 s s -
CC 4 x (CHCONn.STC + 2) x tBC 8 x tBC - -
Data Sheet
95
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 4-6 Parameter Conversion time Electrical Parameters ADC Characteristics (cont'd) (Operating Conditions apply) Symbol Min. Limit Values Typ. Max. s s s LSB LSB LSB LSB LSB LSB LSB LSB nA nA nA nA CC tS + 40 x tBC + 2 x tDIV Unit Test Conditions / Remarks For 8-bit conversion For 10-bit conversion For 12-bit conversion For 8-bit conv. For 10-bit conv. For 12-bit conv.8)9) For 12-bit conv.10)9) For 12-bit conv.12)
9)
tC
tS + 48 x tBC + 2 x tDIV tS + 56 x tBC + 2 x tDIV
Total unadjusted error 5) TUE7) CC - - - - DNL error11)5) INL error11)5) Gain error11)5) Offset error11)5) TUEDNL TUEINL TUEGAIN TUEOFF CC - CC - CC - CC - CC -1000 -200 -200 -200 - - - - 1.5 1.5 0.5 1.0 - 1 2 4 8 3.0 3.0 3.5 4.0 300 400 1000 3000
For 12-bit conv.12)
9)
For 12-bit conv.12)
9)
For 12-bit conv.12)
9)
Input leakage IOZ114) current at analog inputs AN0, AN1 and AN31. see Figure 4-313)
(0% VDDM) < VIN < (2% VDDM) (2% VDDM) < VIN < (95% VDDM) (95% VDDM) < VIN < (98% VDDM) (98% VDDM) < VIN < (100% VDDM)
Data Sheet
96
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 4-6 Parameter Input leakage current at analog inputs AN2 to AN30, see Figure 4-3 Electrical Parameters ADC Characteristics (cont'd) (Operating Conditions apply) Symbol Min. Limit Values Typ. - Max. 200 300 1000 3000 - 1 nA nA nA nA A CC -1000 -200 -200 -200 Input leakage current at VAREF Unit Test Conditions / Remarks (0% VDDM) < VIN < (2% VDDM) (2% VDDM) < VIN < (95% VDDM) (95% VDDM) < VIN < (98% VDDM) (98% VDDM) < VIN < (100% VDDM) 0 V < VAREF < VDDM, no conversion running 0 V < VAREF <
IOZ1
14)
IOZ2
CC -
Input current at
VAREF
17)
IAREF
CC - CC -
35 -
75 25
A rms pF
VDDM15)
9)
Total capacitance CAREFTOT of the voltage reference inputs16)17) Switched CAREFSW capacitance at the positive reference voltage input 17) Resistance of the RAREF reference voltage input path16) Total capacitance CAINTOT of the analog inputs16) Switched capacitance at the analog voltage inputs
CC -
15
20
pF
9)18)
CC -
1
1.5
k
500 Ohm increased for AN[1:0] used as reference input 9)
6)9)
CC -
-
25
pF
CAINSW
CC -
-
7
pF
9)19)
Data Sheet
97
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 4-6 Parameter ON resistance of the transmission gates in the analog voltage path Electrical Parameters ADC Characteristics (cont'd) (Operating Conditions apply) Symbol Min. Limit Values Typ. 1 Max. 1.5 k CC - Unit Test Conditions / Remarks
9)
RAIN
ON resistance for RAIN7T the ADC test (pull-down for AIN7) Current through IAIN7T resistance for the ADC test (pulldown for AIN7)
CC 200
300
1000
Test feature available only for AIN7
9)
CC -
15 rms
30 peak
mA
Test feature available only for AIN7
9)
1) Voltage overshoot to 4 V are permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 2) Voltage overshoot to 1.7 V are permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 3) A running conversion may become inexact in case of violating the normal operating conditions (voltage overshoot). 4) If the reference voltage VAREF increases or the VDDM decreases, so that VAREF = ( VDDM + 0.05 V to VDDM + 0.07 V), then the accuracy of the ADC decreases by 4LSB12. 5) If a reduced reference voltage in a range of VDDM/2 to VDDM is used, then the ADC converter errors increase. If the reference voltage is reduced with the factor k (k<1), then TUE, DNL, INL Gain and Offset errors increase with the factor 1/k. If a reduced reference voltage in a range of 1 V to VDDM/2 is used, then there are additional decrease in the ADC speed and accuracy. 6) Current peaks of up to 6 mA with a duration of max. 2 ns may occur 7) TUE is tested at VAREF = 3.3 V, VAGND = 0 V and VDDM = 3.3 V 8) ADC module capability. 9) Not subject to production test, verified by design / characterization. 10) Value under typical application conditions due to integration (switching noise, etc.). 11) The sum of DNL/INL/Gain/Offset errors does not exceed the related TUE total unadjusted error. 12) For 10-bit conversions the DNL/INL/Gain/Offset error values must be multiplied with factor 0.25. For 8-bit conversions the DNL/INL/Gain/Offset error values must be multiplied with 0.0625. 13) The leakage current definition is a continuous function, as shown in Figure 4-3. The numerical values defined determine the characteristic points of the given continuous linear approximation - they do not define step function. 14) Only one of these parameters is tested, the other is verified by design characterization.
Data Sheet
98
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
15) IAREF_MAX is valid for the minimum specified conversion time. The current flowing during an ADC conversion with a duration of up to tC = 25s can be calculated with the formula IAREF_MAX = QCONV/tC. Every conversion needs a total charge of QCONV = 150pC from VAREF. All ADC conversions with a duration longer than tC = 25s consume an IAREF_MAX = 6A. 16) For the definition of the parameters see also Figure 4-2. 17) Applies to AIN0 and AIN1, when used as auxiliary reference inputs. 18) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this smaller capacitances are successively switched to the reference voltage. 19) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before the sampling moment. Because of the parasitic elements the voltage measured at AINx is lower then VAREF/2.
A/D Converter Module F ractional D ivider
fCLC
fDIV
Program able m C lock D ivider (1:1) to (1:256)
fBC
1:4
fANA
Program able m C ounter
Sam ple T e tS im
C .C C ON T Arbiter (1:20)
C C n.ST H ON C C ontrol/Status Logic Interrupt Logic External T rigger Logic External M ultiplexer Logic R equest Generation Logic
fTIMER
C ontrol U nit (T er) im
M A04657_m C od
Figure 4-1
ADC0 Clock Circuit
Data Sheet
99
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
REXT
ANx
RAIN, On
Analog Input Circuitry
VAIN =
CEXT CAINTOT - CAINSW VAGNDx RAIN7T
CAINSW
Reference Voltage Input Circuitry
VAREFx VAREF VAGNDx
RAREF, On
CAREFTOT - CAREFSW
CAREFSW
Analog_InpRefDiag
Figure 4-2
ADC0 Input Circuits
Data Sheet
100
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
Ioz1 3uA
AN0, AN1 and AN31
1uA 400nA 300nA -200nA -1uA Ioz1 3uA AN2 to AN30 1uA 300nA 200nA -200nA -1uA VIN[VDDM%] 2% 95% 98%100% VIN[VDDM%] 2% 95% 98% 100%
Figure 4-3
ADC0 Analog Inputs Leakage
Data Sheet
101
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.2.3
Fast Analog to Digital Converter (FADC)
Table 4-7 provides the characteristics of the FADC module in the TC1163/TC1164. Table 4-7 Parameter DNL error INL error Gradient error1)12) FADC Characteristics (Operating Conditions apply) Symbol Limit Values Min. Max. 1 4 3 5 6 204) 60
4)
Unit LSB LSB % % % mV mV mV nA nA nA nA V V V V V V
Remarks Conditions
12) 12) 2)
EDNL EINL EGRAD
CC - CC - CC - - -
With calibration, gain 1, 2
Without calibration gain 1, 2, 4 Without calibration gain 8
2)
Offset error12) Reference error of internal VFAREF/2
EOFF3) EREF
CC - - CC - CC -1000 -200 -200 -200
With calibration
Without calibration - (0% VDDM) < VIN < (2% VDDM) (2% VDDM) < VIN < (95% VDDM) (95% VDDM) < VIN < (98% VDDM) (98% VDDM) < VIN < (100% VDDM) - - - Nominal 3.3 V - -
60 300 400 1000 3000 3.477) 1.588) 0.1 3.477)9)
Input leakage current IOZ16) at analog inputs AN32 to AN35. 5) see Figure 4-5
Analog supply voltages Analog ground voltage Analog reference voltage Analog reference ground
VDDMF VDDAF VSSAF
SR 3.13 SR 1.42 SR -0.1
VFAREF SR 3.13 VFAGND SR VSSAF 0.05V SR VFAGND
VSSAF
+0.05V
Analog input voltage VAINF range
Data Sheet
VDDMF
102
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 4-7 Parameter Analog supply currents Electrical Parameters FADC Characteristics (cont'd)(Operating Conditions apply) Symbol SR - SR - CC - CC - CC CC - CC - CC 100 Limit Values Min. Max. 9 17 150 500 8 21 80 200 mA mA A rms nA A CLK of For 10-bit conv. Unit Remarks Conditions -
10)
IDDMF IDDAF Input current at each IFAREF VFAREF Input leakage current IFOZ2 at VFAREF11) Input leakage current IFOZ3 at VFAGND Conversion time tC
Converter Clock Input resistance of the analog voltage path (Rn, Rp) Channel Amplifier Cutoff Frequency Settling Time of a Channel Amplifier after changing ENN or ENP
Independent of conversion 0 V < VIN < VDDMF
fADC fADC RFAIN
MHz k -
12)
fCOFF tSET
CC 2 CC 5
MHz sec
- -
1) Calibration of the gain is possible for the gain of 1 and 2, and not possible for the gain of 4 and 8. 2) Callibration should be performed at each power-up. In case of continuous operation, callibration should be performed minimum once per week. 3) The offset error voltage drifts over the whole temperature range typically 2 LSB. 4) Applies when the gain of the channel equals one. For the other gain settings, the offset error increases; it must be multiplied with the applied gain. 5) The leakage current definition is a continuous function, as shown in Figure 4-5. The numerical values defined determine the characteristic points of the given continuous linear approximation - they do not define step function. 6) Only one of these parameters is tested, the other is verified by design characterization. 7) Voltage overshoot to 4 V are permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 8) Voltage overshoot to 1.7 V are permissible, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 9) A running conversion may become inexact in case of violating the normal operating conditions (voltage overshoots). 10) Current peaks of up to 40 mA with a duration of max. 2 ns may occur
Data Sheet
103
V1.0, 2008-04
TC1163/TC1164
Preliminary
11) This value applies in power-down mode. 12) Not subject to production test, verified by design / characterization.
Electrical Parameters
The calibration procedure should run after each power-up, when all power supply voltages and the reference voltage have stabilized. The offset calibration must run first, followed by the gain calibration.
FADC Analog Input Stage RN FAINxN VFAREF /2
+
VFAGND
RP FAINxP
-
FADC Reference Voltage Input Circuitry VFAREF VFAREF VFAGND IFAREF
=
+
FADC_InpRefDiag
Figure 4-4
FADC Input Circuits
Data Sheet
104
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
Ioz1 3uA AN32 to AN35
1uA 400nA 300nA -200nA -1uA VIN[VDDM%] 2% 95% 98%100%
Figure 4-5
Analog Inputs AN32-AN35 Leakage
Data Sheet
105
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.2.4
Oscillator Pins
Table 4-8 provides the characteristics of the oscillator pins in the TC1163/TC1164. Table 4-8 Parameter Frequency Range Input low voltage at XTAL11) Input high voltage at XTAL11) Oscillator Pins Characteristics (Operating Conditions apply) Symbol Min. Limit values Max. 25 0.3 x MHz - V V A - - 0 V < VIN < VDDOSC3 Unit Test Conditions
fOSC VILX VIHX
CC 4 SR -0.2 SR 0.7 x
VDDOSC3 VDDOSC3
+ 0.2 25
VDDOSC3
CC -
Input current at XTAL1 IIX1
1) If the XTAL1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.3 x VDDOSC3 is necessary.
Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier.
Data Sheet
106
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.2.5
Temperature Sensor
Table 4-9 provides the characteristics of the temperature sensor in the TC1163/TC1164. Table 4-9 Parameter Temperature Sensor Characteristics (Operating Conditions apply) Symbol Min. Temperature TSR Sensor Range Start-up time after resets inactive Temperature of the die at the sensor location Sensor Inaccuracy SR -40 Limit Values Max. 150 10 C s - Unit Remarks
tTSST SR
TTS
CC TTS = (ADC_Code - 487) x 0.396 - 40
C
10-bit ADC result 12Bit ADC result
TTS = (ADC_Code - 1948) x 0.099 - 40 C TTSA CC
SR - 10 10 C
A/D Converter fANA clock for DTS signal
MHz Conversion with ADC0
Data Sheet
107
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.2.6
Power Supply Current
Table 4-10 provides the characteristics of the power supply current in the TC1163/TC1164. Table 4-10 Parameter Power Supply Current (Operating Conditions apply) Symbol Limit Values Min. Typ. Max. PORST low current at Unit Test Conditions / Remarks mA The PLL running at the base frequency The PLL running at the base frequency
IDD_PORST
CC
-
-
63
VDD
PORST low current at
IDDP_PORST CC
-
-
5
mA
VDDP
Active mode core supply current1) Active mode analog supply current Oscillator and PLL core power supply Oscillator and PLL pads power supply FLASH power supply current LVDS port supply (via VDDP)3) Maximum Allowed Power Dissipation4)
IDD IDDAx; IDDMx IDDOSC IDDOSC3 IDDFL3 ILVDS PDmax
CC CC CC CC CC CC SR
- - - - - -
- - - - - -
260 - 5 3.62) 45 25
mA mA mA mA mA mA -
fCPU = 80MHz fCPU/fSYS = 1:1
See ADC0/FADC - - - LVDS pads active At worst case, TA = 85 C
PD x RTJA < 40C
1) Infineon Power Loop: CPU running, all peripherals active. The power consumption of each custom application will most probably be lower than this value, but must be evaluated separately. 2) Estimated value; double-bonded at package level with VDDP. 3) In case the LVDS pads are disabled, the power consumption per pair is negligible (less than 1mA). 4) For the calculation of the junction to ambient thermal resistance RTJA, see Chapter 5.1.
Data Sheet
108
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.3
AC Parameters
All AC parameters are defined with the temperature compensation disabled, which means that pads are constantly kept at the maximum strength.
4.3.1
Testing Waveforms
The testing waveforms for rise/fall time, output delay and output high impedance are shown in Figure 4-6, Figure 4-7 and Figure 4-8.
VDDP 90% 90%
VSS
10% tR tF
10%
rise_fall
Figure 4-6
Rise/Fall Time Parameters
VDDP VDDE / 2 VSS
Mct04881_LL.vsd
Test Points
VDDE / 2
Figure 4-7
Testing Waveform, Output Delay
VLoad + 0.1 V VLoad - 0.1 V
Timing Reference Points
VOH - 0.1 V VOL - 0.1 V
MCT04880_LL
Figure 4-8
Testing Waveform, Output High Impedance
Data Sheet
109
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.3.2
Output Rise/Fall Times
Table 4-11 provides the characteristics of the output rise/fall times in the TC1163/TC1164. Table 4-11 Parameter Class A1 Pads Rise/fall times1) Class A1 pads Output Rise/Fall Times (Operating Conditions apply) Symbol Limit Values Unit Test Conditions Min. Max. 50 140 18000 150 550 65000 3.3 6 5.5 16 50 140 18000 150 550 65000 2.5 ns Regular (medium) driver, 50 pF Regular (medium) driver, 150 pF Regular (medium) driver, 20 nF Weak driver, 20 pF Weak driver, 150 pF Weak driver, 20 000 pF Strong driver, sharp edge, 50 pF Strong driver, sharp edge, 100pF Strong driver, med. edge, 50 pF Strong driver, soft edge, 50 pF Medium driver, 50 pF Medium driver, 150 pF Medium driver, 20 000 pF Weak driver, 20 pF Weak driver, 150 pF Weak driver, 20 000 pF 50 pF
tRA1, tFA1
Class A2 Pads Rise/fall times 1) Class A2 pads tFA2, tFA2 ns
Class A3 Pads Rise/fall times 1) Class A3 pads Class A4 Pads Rise/fall times 1) Class A4 pads Class C Pads Rise/fall times Class C pads tFA4, tFA4 2.0 ns 25 pF tFA3, tFA3 ns
trC, tfC
2
ns
1) Not all parameters are subject to production test, but verified by design/characterization and test correlation.
Data Sheet
110
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.3.3
Power Sequencing
There is a restriction for the power sequencing of the 3.3 V domain as shown in Figure 4-9. It must always be higher than 1.5 V domain - 0.5 V. The gray area shows the valid range for V3.3V relative to an exemplary V1.5V ramp. VDDP, VDDOSC3, VDDM, VDDMF, VDDFL3 belong to the 3.3 V domain. The VDDM and VDDMF subdomains are connected with antiparallel ESD protection diodes. There are no other such connections between the subdomains. VDD , VDDOSC and VDDAF belong to the 1.5 V domain.
Power Supply Voltage
3.3V V3 .3 V1 .5
V al
3. 3
V
id a
id a re a fo r
1.5V
re a
.3 for V 3
V al
V 3 .3 > V1 .5 - 0.5V
Time
VD D P (3.3V) PORST
Time PowerSeq
Figure 4-9
Power Up Sequence
All ground pins VSS must be externally connected to one single star point in the system. The difference voltage between the ground pins must not exceed 200 mV. The PORST signal must be activated at latest before any power supply voltage falls below the levels shown on the figure below. In this case, only the memory row of a Flash memory that was the target of the write at the moment of the power loss will contain unreliable content. Additionally, the PORST signal should be activated as soon as possible. The sooner the PORST signal is activated, the less time the system operates outside of the normal operating power supply range.
Data Sheet
111
V1.0, 2008-04
TC1163/TC1164
Preliminary
Power Supply Voltage
Electrical Parameters
VDDP VDDPmin VPORST3.3
3.3V 3.13V
VDDP -5%
2.9V
-12%
t
PORST
t
VDD V PORST1.5min V DDmin
1.5V
V DD
1.42V 1.32V
-5% -12%
t
PORST
PowerDown3.3_1.5_reset_only_LL.vsd
t
Figure 4-10 Power Down / Power Loss Sequence
Data Sheet
112
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.3.4
Power, Pad and Reset Timing
Table 4-12 provides the characteristics of the power, pad and reset timing in the TC1163/TC1164. Table 4-12 Parameter Min. VDDP voltage to ensure defined pad states1) Oscillator start-up time2) Minimum PORST active time after power supplies are stable at operating levels HDRST pulse width PORST rise time Setup time to PORST rising edge4) Hold time from PORST rising edge4) Setup time to HDRST rising edge5) Hold time from HDRST rising edge5) Ports inactive after PORST reset active6)7) Ports inactive after HDRST reset active8) Minimum VDDP PORST activation threshold.9) Minimum VDD PORST activation threshold. 9) Power-on Reset Boot Time10) Hardware/Software Reset Boot Time at fCPU=80MHz11) Power, Pad and Reset Timing Parameters Symbol Min. Limit Values Max. - 10 - V ms ms CC 0.6 CC - SR 10 Unit
VDDPPA tOSCS tPOA
tHD tPOR tPOS tPOH tHDS tHDH tPIP tPI
CC 1024 clock cycles3) SR - SR 0 SR 100 SR 0 SR 100 + (2 x 1/fSYS) CC - CC -
- 50 - - - - 150 150 + 5 x 1/fSYS 2.9 1.32 3.50 800
fSYS
ms ns ns ns ns ns ns V V ms s
VPORST3.3 SR - VPORST1.5 SR - tBP tB
CC 2.15 CC 500
1) This parameter is valid under assumption that PORST signal is constantly at low-level during the powerup/power-down of the VDDP. 2) This parameter is verified by device characterization. The external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended and specified by crystal suppliers. 3) Any HDRST activation is internally prolonged to 1024 FPI bus clock (fSYS) cycles.
Data Sheet
113
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4) Applicable for input pins TESTMODE, TRST, BRKIN, and TXD1A with noise suppression filter of PORST switched-on (BYPASS = 0). 5) The setup/hold values are applicable for Port 0 and Port 4 input pins with noise suppression filter of HDRST switched-on (BYPASS = 0), independently whether HDRST is used as input or output. 6) Not subject to production test, verified by design / characterization. 7) This parameter includes the delay of the analog spike filter in the PORST pad. 8) Not subject to production test, verified by design / characterization. 9) In case of power loss during internal flash write, prevents Flash write to random address. 10) Booting from Flash, the duration of the boot-time is defined between the rising edge of the PORST and the moment when the first user instruction has entered the CPU and its processing starts. 11) Booting from Flash, the duration of the boot time is defined between the following events: 1. Hardware reset: the falling edge of a short HDRST pulse and the moment when the first user instruction has entered the CPU and its processing starts, if the HDRST pulse is shorter than 1024 x TSYS. If the HDRST pulse is longer than 1024 x TSYS, only the time beyond the 1024 x TSYS should be added to the boot time (HDRST falling edge to first user instruction). 2. Software reset: the moment of starting the software reset and the moment when the first user instruction has entered the CPU and its processing starts
VDDPPA VDDP
VDDPPA
VDD
toscs
VDDPR
OSC tPOA tPOA PORST thd HDRST 2) Padstate undefined 1) t pi 1) as programmed 2) Tri-state, pull device active
reset_beh
thd
Pads
2)
1)
2) Padstate undefined
Figure 4-11 Power, Pad and Reset Timing
Data Sheet
114
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.3.5
Phase Locked Loop (PLL)
Section 4.3.5 provides the characteristics of the PLL parameters and its operation in the TC1163/TC1164. Note: All PLL characteristics defined on this and the next page are verified by design characterization. Table 4-13 Parameter Accumulated jitter VCO frequency range PLL Parameters (Operating Conditions apply) Symbol Limit Values Min. Max. - MHz MHz MHz MHz MHz MHz s 500 600 700 320 400 480 200 See Figure 4-12 400 500 600 PLL base frequency1) Unit
DP fVCO
fPLLBASE
140 150 200
PLL lock-in time
tL
-
1) The CPU base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is the K factor after reset).
Phase Locked Loop Operation When PLL operation is enabled and configured, the PLL clock fVCO (and with it the CPU clock fCPU) is constantly adjusted to the selected frequency. The relation between fVCO and fSYS is defined by: fVCO = K x fCPU. The PLL causes a jitter of fCPU and affects the clock outputs TRCLK and SYSCLK (P4.3) which are derived from the PLL clock fVCO. There are two formulas that define the (absolute) approximate maximum value of jitter DP in ns dependent on the K-factor, the CPU clock frequency fCPU in MHz, and the number P of consecutive fCPU clock periods. P x K < 900 P x K 900 5xP Dp [ ns ] = ----------------------------- + 0, 9 fcpu [ MHz ] 4500 Dp [ ns ] = --------------------------------------- + 0, 9 fcpu [ MHz ] x K (4.1) (4.2)
K : K-Divider Value P : Number of fCPU periods
DP : Jitter in ns fCPU : CPU frequency in MHz
Data Sheet 115 V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
Note: The frequency of system clock fSYS can be selected to be either fCPU or fCPU/2. With rising number P of clock cycles the maximum jitter increases linearly up to a value of P that is defined by the K-factor of the PLL. Beyond this value of P the maximum accumulated jitter remains at a constant value. Further, a lower CPU clock frequency fCPU results in a higher absolute maximum jitter value. Figure 4-12 illustrates the jitter curve for several K/ fCPU combinations.
TC1163/TC1164 PLL Jitter (Preliminary) Jit ter [n s] 13.0
12.0 fCP U = 40 MHz (K = 10) 11.0 fCP U = 80 MHz (K = 5)
10.0
fCP U = 66 MHz ( K = 7)
9.0 fCP U = 40 MHz (K = 17) 8.0 fCP U = 80 MHz (K = 8)
7.0
fCP U = 66 MHz (K = 10)
6.0
5.0
4.0
3.0
2.0
1.0
0.0 1 25 50 75 100 125 150 175 oo P [Periods]
TC1163/TC1164 PLL Jitter
Figure 4-12 Approximated Maximum Accumulated PLL Jitter for Typical CPU Clock Frequencies fCPU (overview)
Data Sheet 116 V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
TC1163/TC1164 PLL Jitter (preliminary )
Jitter [ns]
1.40 1.30 1.20 1.10 1.00 0.90
fCP U = 40 MHz f CP U = 66 MHz
fCP U = 80 MHz
1
2
3
4 5 P [Periods]
TC1163/TC1164 PLL Jitter -Detail
Figure 4-13 Approximated Maximum Accumulated PLL Jitter for Typical CPU Clock Frequencies fCPU (detail) Note: The maximum peak-to-peak noise on the main oscillator and PLL power supply (measured between VDDOSC and VSSOSC) is limited to a peak-to-peak voltage of VPP = 10 mV. This condition can be achieved by appropriate blocking to the supply pins and using PCB supply and ground planes.
Data Sheet
117
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.3.6
Debug Trace Timing
VSS = 0 V; VDDP = 3.13 to 3.47 V (Class A); TA = -40 C to +85 C; CL (TRCLK) = 25 pF; CL (TR[15:0]) = 50 pF
Table 4-14 Parameter TR[15:0] new state from TRCLK Debug Trace Timing Parameter1) Symbol Min. Limit Values Max. 4 ns CC -1 Unit
t9
1) Not subject to production test, verified by design/characterization.
TRCLK
t9
TR[15:0] Old State New State
Trace_Tmg
Figure 4-14 Debug Trace Timing
Data Sheet
118
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.3.7
Timing for JTAG Signals
(Operating Conditions apply, CL = 50 pF) Table 4-15 Parameter TCK clock period1) TCK high time TCK low time TCK clock rise time TCK clock fall time
1) fTCK should be lower or equal to fSYS
TCK Clock Timing Parameter Symbol Min. Limit Values Max. - - - 4 4 ns ns ns ns ns SR 25 SR 10 SR 10 SR - SR - Unit
tTCK t1 t2 t3 t4
0.5 VDD
0.9 VDD 0.1 VDD
TCK
t1 tTCK t2 t4 t3
Figure 4-15 TCK Clock Timing
Data Sheet
119
V1.0, 2008-04
TC1163/TC1164
Preliminary Table 4-16 Parameter JTAG Timing Parameter1) Symbol Limit Values Min. Max. TMS setup to TCK TMS hold to TCK TDI setup to TCK TDI hold to TCK TDO valid output from TCK2) TDO high impedance to valid output from TCK2) TDO valid output to high impedance from TCK2) - - - - 14.5 - 15.5 ns Unit Test Conditions / Remarks - - - - CL = 50 pF3)4) CL = 20 pF CL = 50 pF3)4) CL = 50 pF4) Electrical Parameters
t1 t2 t1 t2 t3 t4 t5
SR 6.0 SR 6.0 SR 6.0 SR 6.0 CC - 3.0 CC -
ns ns ns ns ns
CC -
14.5
ns
1) Not subject to production test, verified by design / characterization. 2) The falling edge on TCK is used to capture the TDO timing. 3) By reducing the load from 50 pF to 20 pF, a reduction of approximately 1.0 ns in timing is expected. 4) By reducing the power supply range from +/-5 % to +5/-2 %, a reduction of approximately 0.5 ns in timing is expected.
Data Sheet
120
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
TCK
t1
t2
TMS
t1
t2
TDI
t4 t3 t5
TDO
Figure 4-16 JTAG Timing Note: The JTAG module is fully compliant with IEEE1149.1-2000 with JTAG clock at 20 MHz. The JTAG clock at 40 MHz is possible with the modified timing diagram shown in Figure 4-16.
Data Sheet
121
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.3.8
Peripheral Timings
Section 4.3.8 provides the characteristics of the peripheral timings in the TC1163/TC1164. Note: Peripheral timing parameters are not subject to production test. They are verified by design/characterization.
4.3.8.1
Micro Link Interface (MLI) Timing
Table 4-17 provides the characteristics of the MLI timing in the TC1163/TC1164. Table 4-17 Parameter TCLK clock period
1)2)
MLI Timing (Operating Conditions apply, CL = 50 pF) Symbol Limit Values Min. Max. - - 8 - - 8 1/fSYS 1/fSYS ns ns ns ns CC SR CC SR SR CC 2 1 0 4 4 0
3)
Unit
RCLK clock period MLI outputs delay from TCLK MLI inputs setup to RCLK MLI inputs hold to RCLK RREADY output delay from RCLK
t30 t31 t35 t36 t37 t38
1) TCLK signal rise/fall times are the same as the A2 Pads rise/fall times. 2) TCLK high and low times can be minimum 1 x TMLI 3) TMLImin = TSYS = 1/fSYS. When fSYS = 80MHz, t30 = 25ns
Data Sheet
122
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
t30
TCLKx 0.9 VDDP 0.1 VDDP
t35
TDATAx TVALIDx
t35
TREADYx
t30
RCLKx
t36
RDATAx RVALIDx
t37
t38
RREADYx
t38
MLI_Tmg_1.vsd
Figure 4-17 MLI Interface Timing Note: The generation of RREADYx is in the input clock domain of the receiver. The reception of TREADYx is asynchronous to TCLKx.
Data Sheet
123
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.3.8.2
Micro Second Channel (MSC) Interface Timing
Table 4-18 provides the characteristics of the MSC timing in the TC1163/TC1164. Table 4-18 Parameter FCLP clock period1)2) SOP/ENx outputs delay from FCLP SDI bit time SDI rise time SDI fall time
2) FCLP signal high and low can be minimum 1 x TMSC. 3) TMSCmin = TSYS = 1/fSYS. When fSYS = 80MHz, t40 = 25ns
MSC Interface Timing (Operating Conditions apply, CL = 50 pF) Symbol Min. Limit Values Max. - 10 - 100 100 ns ns ns ns ns Unit
t40 t45 t46 t48 t49
CC 2 x TMSC3) CC -10 SR 8 x TMSC SR SR
1) FCLP signal rise/fall times are the same as the A2 Pads rise/fall times.
t40
FCLP 0.9 VDDP 0.1 VDDP
t45
SOP EN
t 45
t48
SDI
t 49
0.9 VDDP 0.1 VDDP
t46
t46
MSC_Tmg_1.vsd
Figure 4-18 MSC Interface Timing Note: The data at SOP should be sampled with the falling edge of FCLP in the target device.
Data Sheet
124
V1.0, 2008-04
TC1163/TC1164
Preliminary Electrical Parameters
4.3.8.3
Synchronous Serial Channel (SSC) Master Mode Timing
Table 4-19 provides the characteristics of the SSC timing in the TC1163/TC1164. Table 4-19 Parameter SCLK clock period1)2) MTSR/SLSOx delay from SCLK MRST setup to SCLK MRST hold from SCLK SSC Master Mode Timing (Operating Conditions apply, CL = 50 pF) Symbol Min. Limit Values Max. - 8 - - ns ns ns ns Unit
t50 t51 t52 t53
CC 2 x TSSC3) CC 0 SR 10 SR 5
1) SCLK signal rise/fall times are the same as the A2 Pads rise/fall times. 2) SCLK signal high and low times can be minimum 1 x TSSC. 3) TSSCmin = TSYS = 1/fSYS. When fSYS = 80 MHz, t50 = 25ns
t50
SCLK1)2)
t51
MTSR1)
t51
t52
MRST1)
t53
Data valid
t51
SLSOx2)
1) This timing is based on the following setup: CON.PH = CON.PO = 0. 2) The transition at SLSOx is based on the following setup: SSOTC.TRAIL = 0 and the first SCLK high pulse is in the first one of a transmission. SSC_Tmg_1.vsd
Figure 4-19 SSC Master Mode Timing
Data Sheet
125
V1.0, 2008-04
TC1163/TC1164
Preliminary Package and Reliability
5
Package and Reliability
Chapter 5 provides the information of the TC1163/TC1164 package and reliability section.
5.1
Table 5-1 Parameter
Package Parameters (PG-LQFP-176-2)
Thermal Characteristics of the Package Symbol Limit Values Min. Max. 5.4 21.5 K/W - K/W - - - Unit Notes
Table 5-1 provides the thermal characteristics of the package.
Thermal resistance junction case top1) Thermal resistance junction leads1)
RTJCT CC RTJL
CC
1) The thermal resistances between the case top and the ambient (RTCAT), the leads and the ambient (RTLA) are to be combined with the thermal resistances between the junction and the case top (RTJCT ), the junction and the leads (RTJL) given above, in order to calculate the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the case top and the ambient (RTCAT ), the leads and the ambient (RTLA) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: TJ=TA+RTJA x PD, where the RTJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances.
Data Sheet
126
V1.0, 2008-04
TC1163/TC1164
Preliminary Package and Reliability
5.2
Package Outline
Figure 5-1 shows the package outlines of the TC1163/TC1164. PG-LQFP-176-2 Plastic Low Profile Quad Flat Package
Figure 5-1
Package Outlines PG-LQFP-176-2
You can find all of our packages, sorts of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products.
SMD = Surface Mounted Device Data Sheet 127
Dimensions in mm
V1.0, 2008-04
TC1163/TC1164
Preliminary Package and Reliability
5.3
Flash Memory Parameters
The data retention time of the TC1163/TC1164's Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Table 5-2 Parameter Program Flash Retention Time, Physical Sector1)2) Program Flash Retention Time, Logical Sector1)2) Data Flash Endurance (128 Kbyte) Data Flash Endurance, EEPROM Emulation (8 x 16 Kbyte) Programming Time per Page3) Program Flash Erase Time per 256-Kbyte sector Data Flash Erase Time per 16-Kbyte sector Wake-up time Flash Parameters Symbol Limit Values Min. Max. - years Max. 1000 erase/program cycles Max. 50 erase/program cycles Max. data retention time 2 years Max. data retention time 2 years - 15 Unit Notes
tRET
tRETL
15
-
years
NE NE8
15 000 120 000
- -
- -
tPR tERP
- -
5 5
ms s
fCPU = 80 MHz
tERD tWU
-
0.625
s
fCPU = 80 MHz
4300 x 1/fCPU + 40s
1) Storage and inactive time included. 2) At average weighted junction temperature TJ = 100 C. 3) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The reprogramming takes additional 5ms.
Data Sheet
128
V1.0, 2008-04
TC1163/TC1164
Preliminary Package and Reliability
5.4
Table 5-3 Parameter
Quality Declaration
Quality Parameters Symbol - Limit Values Min. Max. 2000 V Conforming to EIA/JESD22A114-B - Conforming to JESD22-C101-C Conforming to J-STD-020C for 240C Unit Notes
Table 5-3 shows the characteristics of the quality parameters in the TC1163/TC1164.
ESD susceptibility VHBM according to Human Body Model (HBM) ESD susceptibility of the LVDS pins
VHBM1
- -
500 500
V V
ESD susceptibility VCDM according to Charged Device Model (CDM) pins Moisture Sensitivity Level - (MSL)
-
3
-
Note: Information about soldering can be found on the "package" information page under: http://www.infineon.com/products.
Data Sheet
129
V1.0, 2008-04
www.infineon.com
Published by Infineon Technologies AG

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